求助啊，加不进去约束条件，急啊。 模块, 条件

lucsunny

vout5.zip (849.41 KB)

下载次数: 193

2011-7-27 16:07

我用原理图输入的方式，使用了ISE里面的inv4模块，然后编译的时候都正确，自动分配了管脚。现在我在里面加入管脚的约束条件就不对了，大家帮帮忙，怎么处理啊。

lucsunny

是我的UCF文件编写不合理吗，没有区分出层次出来么？

savagezp

Considering device XC9572XL-10-VQ44.
ERROR:Cpld:832 - 'DIN2' is assigned to an invalid location ('P4') for this device.  This will prevent the design from fitting on the current device. 'DIN2' must be reassigned before attempting a re-fit.
ERROR:Cpld:832 - 'DIN3' is assigned to an invalid location ('P10') for this device.  This will prevent the design from fitting on the current device. 'DIN3' must be reassigned before attempting a re-fit.
ERROR:Cpld:832 - 'GPIO20' is assigned to an invalid location ('P17') for this device.  This will prevent the design from fitting on the current device. 'GPIO20' must be reassigned before attempting a re-fit.
ERROR:Cpld:832 - 'GPIO21' is assigned to an invalid location ('P15') for this device.  This will prevent the design from fitting on the current device. 'GPIO21' must be reassigned before attempting a re-fit.
ERROR:Cpld:832 - 'PWM2A' is assigned to an invalid location ('P9') for this device.  This will prevent the design from fitting on the current device. 'PWM2A' must be reassigned before attempting a re-fit.
ERROR:Cpld:832 - 'PWM2B' is assigned to an invalid location ('P11') for this device.  This will prevent the design from fitting on the current device. 'PWM2B' must be reassigned before attempting a re-fit.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options.

savagezp

Description
Keywords: 5.2i, 5.1i, 4.2i, 4.1i, error, CPLD, assigned, invalid, location, device, pin

Urgency: Standard

General Description:
When I run implementation in Project Navigator, a message similar to one of the following occurs:

"ERROR:CPLD:832 - 'net' is assigned to an invalid location ('PX') for this device. This will prevent the design from fitting on the current device. 'net' must be reassigned before attempting a re-fit."

"ERROR:Cpld:6 - Cannot assign Output Pin moda to PX* (FB1_4). This pin does not support the functionality of that signal."

*PX - X is a pin number.


Solution
To solve this problem, check the following:

- Check the device data sheet to see if "PX" is a dedicated pin that cannot be used for I/O (e.g., JTAG pin, VCC, GND, etc.)
- Ensure that you are using the proper notation for location constraints:
a) Example for pinned packages (PC, VQ, TQ, HQ), where "y" is the pin number:
NET DATAIN LOC = Py;
b) Example for ball-grid packages (FG, BG, CS), where "x" is the row letter and "y" is the column number:
NET DATAIN LOC = xy;
- Be sure that you have not placed a PROHIBIT constraint on that same location.

Data sheets are available at:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

CoolRunner XPLA3 Only
If you are attempting to utilize the JTAG pins as I/O, ensure that you have de-selected "Reserve ISP Pins" in the software.