1.1 Overview Timemultiplex hardware dynamically on a single FPGA is advantageous:
figure1.1 Basic Premise of Partial Reconfiguration Aftera full BIT file configures the FPGA, partial BIT files can be downloaded tomodify reconfigurable regions in the FPGA without compromising the integrity ofthe applications running on those parts of the device that are not beingreconfigured.
Partial Reconfiguration is time multiplex ,and it's advantage :
• Reducing the size of the FPGA required to implement a givenfunction, with consequent
reductionsin cost and power consumption
• Providing flexibility in the choices of algorithms or protocolsavailable to an application
• Enabling new techniques in design security
• Improving FPGA fault tolerance
• Accelerating configurable computing
1.2 Design criteriaSome component types can be reconfiguredand some cannot.
For 7 series devices, the component rulesare as follows:
° Reconfigurable resources include CLB,BRAM, and DSP component types as well as
routing resources.
° Clocks and clock modifying logic cannotbe reconfigured, and therefore must reside
in the static region.
- Includes BUFG, BUFR, MMCM, PLL, andsimilar components
° The following components cannot bereconfigured, and therefore must reside in the
static region:
- I/O and I/O related components (ISERDES,OSERDES, IDELAYCTRL)
- Serial transceivers (MGTs) and relatedcomponents
- Individual architecture feature components(such as BSCAN, STARTUP, ICAP,
XADC.)
For UltraScale and UltraScale+ devices, thelist of reconfigurable component types is
more extensive:
° CLB, BRAM, and DSP component types aswell as routing resources
° Clocks and clock modifying logic, includingBUFG, MMCM, PLL, and similar
components
° I/O and I/O related components (ISERDES,OSERDES, IDELAYCTRL)
Note: The types of changes for I/O components is limited. See I/O Rules inChapter 7 for
more information.
° Serial transceivers (MGTs) and relatedcomponents
° PCIe, CMAC, Interlaken, and SYSMON blocks
° Bitstream granularity of these newcomponents require that certain rules are
followed. For example, partialreconfiguration of I/O require that the entire bank,
plus all clocking resources in that frameare reconfigured together.
° Only the configuration components (suchas BSCAN, STARTUP, ICAP, and
FRAME_ECC) must remain in the staticportion of the design.
• Global clocking resources toReconfigurable Partitions are limited, depending on the
device and on the clock regions occupied bythese Reconfigurable Partitions.
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ch.2: Vivado Software Flowprocessing a PR design:
1. Synthesize the static and ReconfigurableModules separately.
2. Create physical constraints (Pblocks) todefine the reconfigurable regions.
3. Set the HD.RECONFIGURABLE property oneach Reconfigurable Partition.
4. Implement a complete design (static andone Reconfigurable Module per
Reconfigurable Partition) in context.
5. Save a design checkpoint for the fullrouted design.
6. Remove Reconfigurable Modules from thisdesign and save a static-only design
checkpoint.
7. Lock the static placement and routing.
8. Add new Reconfigurable Modules to thestatic design and implement this new
configuration, saving a checkpoint for thefull routed design.
9. Repeat Step 8 until all ReconfigurableModules are implemented.
10. Run a verification utility (pr_verify)on all configurations.
11. Create bitstreams for eachconfiguration. |
