这几天一直在调试CAN这部分，自己对协议这块不太理解，所以有点慢，不过找到些资料希望与大家分享，希望对大家有帮助。 >I am puzzled about setting up the CAN bus baud rate registers. I am
> using a 5 MHz crystal and want to end up with a 500 MHz CAN bus.
Typo, should be 500kbps. That's max possible rate for this clock.
> The registers in question are CANBTR0 and CANBTR1. I guess the SJW
> bits don't have any particular effect on bus speed. The BRP bits are
SJW doesn't affect bit time but there are another requirement(s) for min
TSEG1 value etc and you have to solve all of them.
> described as determining the time quanta clock which build up the
> indivdual bit timing. So, for my application, it appears that I need
> to set it to 9 (for divide by 10).
No. Prescaler determines Tq. Minimum number of Tq's in bit time is 8. You
have 5MHz clock, that's 200ns. One bittime for 500kbps is 2us.
2us/200ns=10Tq. Max possible prescaler is 1 in your case. (BRP+1)=2 would
give you only 5Tq's and that wouldn't work because <8Tq.
> Meanwhile, over in CANBTR1, the TSEG bits are all described as
> defining the number of clock cycles per bit time, and the location of
> the sample point. But how does this fit into CANBTR0? Do TSEG20..22
> and TSEG10..13 have to add up to 9? If not, what?
No. Bit time is determined by Tq*(syncseg+ tseg1 + tseg2) . Syncseg
is 1Tq and equation must be 1+ tseg1 +tseg2 =10 in your case. It could be
1+6+3, or maybe 1+5+4. Both variants should work but please examine them
thoroughly. Note that my tseg1 actually is TSEG1 bits +1 so
CANxBTR0 = (SAMP <<7) | ((tseg2-1) <<4) | (tseg1-1) ;
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