请教关于时钟输出的buf问题 时钟, buf, 输出, 请教

laoniao

我在用xilinx的xc4vlx40做一个设计，在implement的时候遇到了这个问题：
Error：Place:906 - Components driven by IO clock net <XLXI_58/top_00/iobs_0/data_path_iobs_0/dqs_bufio_out_w<4>> can't be
   placed and routed because location constraints are causing the clock region rules to be violated. IO Clock net
   <XLXI_58/top_00/iobs_0/data_path_iobs_0/dqs_bufio_out_w<4>> is being driven by BUFIO
   <XLXI_58/top_00/iobs_0/data_path_iobs_0/gen_dqs[4].bufio_dqs> locked to site "BUFIO_X0Y3" Because of this location
   contraint, <XLXI_58/top_00/iobs_0/data_path_iobs_0/dqs_bufio_out_w<4>> can only drive clock regions
   "CLOCKREGION_X0Y2, CLOCKREGION_X0Y1, CLOCKREGION_X0Y0". The following components driven by
   <XLXI_58/top_00/iobs_0/data_path_iobs_0/dqs_bufio_out_w<4>> have been locked to sites outside of these clock regions:
   XLXI_58/top_00/iobs_0/data_path_iobs_0/gen_dq[32].u_iob_dq/ISERDES_dq (Locked Site: ILOGIC_X0Y113 CLOCKREGION_X0Y3)
   XLXI_58/top_00/iobs_0/data_path_iobs_0/gen_dq[34].u_iob_dq/ISERDES_dq (Locked Site: ILOGIC_X0Y101 CLOCKREGION_X0Y3)
   XLXI_58/top_00/iobs_0/data_path_iobs_0/gen_dq[36].u_iob_dq/ISERDES_dq (Locked Site: ILOGIC_X0Y12 CLOCKREGION_X0Y0)
   XLXI_58/top_00/iobs_0/data_path_iobs_0/gen_dq[38].u_iob_dq/ISERDES_dq (Locked Site: ILOGIC_X0Y13 CLOCKREGION_X0Y0)
   XLXI_58/top_00/iobs_0/data_path_iobs_0/gen_dq[33].u_iob_dq/ISERDES_dq (Locked Site: ILOGIC_X0Y118 CLOCKREGION_X0Y3)
   XLXI_58/top_00/iobs_0/data_path_iobs_0/gen_dq[35].u_iob_dq/ISERDES_dq (Locked Site: ILOGIC_X0Y100 CLOCKREGION_X0Y3)
   XLXI_58/top_00/iobs_0/data_path_iobs_0/gen_dq[37].u_iob_dq/ISERDES_dq (Locked Site: ILOGIC_X0Y37 CLOCKREGION_X0Y1)
   XLXI_58/top_00/iobs_0/data_path_iobs_0/gen_dq[39].u_iob_dq/ISERDES_dq (Locked Site: ILOGIC_X0Y5 CLOCKREGION_X0Y0)
   Please evaluate the location constraints of both the BUFIO and the components driven by
   <XLXI_58/top_00/iobs_0/data_path_iobs_0/dqs_bufio_out_w<4>> to ensure that they follow the clock region rules of the
   architecture. For more information on the clock region rules, please refer to the architecture user's guide. To debug
   your design with partially routed design, please allow mapper/placer to finish the execution (by setting environment
   variable XIL_PAR_DEBUG_IOCLKPLACER to 1).
劳烦各位帮小弟看看这个该怎么解决呢？
我的板子都已经做好了，引脚分配都确定了，只能考虑其他的解决办法了，恳请大家指教！