请教fir fir, 请教

cug_zhang

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity largefilter is port ( clock : in std_logic; din0x : in std_logic_vector( 7 downto 0 ); coef0x : in std_logic_vector( 7 downto 0 ); result : out std_logic_vector( 15 downto 0 )); end largefilter; architecture str of largefilter is component filter port ( clock : in std_logic; din0x : in std_logic_vector( 7 downto 0); coef0x : in std_logic_vector( 7 downto 0); din4x : out std_logic_vector( 7 downto 0 ); coef4x : out std_logic_vector( 7 downto 0 ); result : out std_logic_vector( 15 downto 0 )); end component; signal coef4x,din4x,coef8x,din8x,coef12x,din12x,coef16x,din16x : std_logic_vector( 7 downto 0 ); signal r0x,r4x,r8x,r12x : std_logic_vector( 15 downto 0 ); begin filter0 : filter port map ( clock,din0x,coef0x,din4x,coef4x,r0x); filter1 : filter port map ( clock,din4x,coef4x,din8x,coef8x,r4x); filter2 : filter port map ( clock,din8x,coef8x,din12x,coef12x,r8x); filter3 : filter port map ( clock,din12x,coef12x,din16x,coef16x,r12x); process(clock) begin if rising_edge(clock) then result <= r0x + r4x + r8x + r12x ; end if; end process; end str; 这是一个fir滤波器的程序,8bit输入,16bit输出.我想把他改为8bit输入,8bit输出,我该怎摸做?请高手指点一下.谢谢!