[求助]请高手指点 高手, 指点, 求助

jinwh

我用vhdl编写一个模数转换器模块的时候。前仿真通过，综合通过。 在进行后仿真的时候总是得不到正确的结果，比如输出端应该输出0110的时候，不出0110 二是0xx0或者别的数值。请问谁知道是什么原因吗？ 代码如下：library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity Ts is PORT (clk, reset : IN std_logic ; in_1, start : IN std_logic ; da_word: OUT std_logic_vector(3 downto 0); out_S: OUT std_logic_vector(3 downto 0)) ; end Ts; architecture Behavioral of Ts is TYPE fsm_state IS (init, state_1, state_2, state_3) ; SIGNAL state,NEXT_STATE : fsm_state ; SIGNAL Counter:integer ; SIGNAL out_T:std_logic_vector(3 downto 0); begin ClockROCESS (CLK,RESET) BEGIN if(RESET = '0') THEN state<=init; Counter<=0; elsif (CLK ' EVENT AND CLK='1') THEN IF(Start= '1') THEN if(Counter<5) THEN STATE<=NEXT_STATE; COUNTER<=Counter+1; out_s<=out_T; else da_word<=out_T; out_s<=out_T; STATE<=state_1; counter<=1; END IF; ELSE state<=init; END IF; END IF; END PROCESS; scROCESS (STATE,Counter) BEGIN CASE STATE is WHEN State_1 => out_T<="1000"; WHEN STATE_2 => CASE Counter is WHEN 2 => out_T(2)<='1'; WHEN 3 => out_T(1)<='1'; WHEN 4 => out_T(0)<='1'; WHEN 5 => out_T(0)<='1'; WHEN others => out_T<="1111"; END CASE; WHEN STATE_3 => CASE Counter is WHEN 2 => out_T(3)<='0'; out_T(2)<='1'; WHEN 3 => out_T(2)<='0'; out_T(1)<='1'; WHEN 4 => out_T(1)<='0'; out_T(0)<='1'; WHEN 5 => out_T(0)<='0'; WHEN others => out_T<="1000"; END CASE; WHEN Others => out_T<="0000"; END CASE; END PROCESS; StROCESS(STATE,in_1) BEGIN NEXT_STATE<=STATE; CASE STATE is WHEN STATE_1 => IF(In_1 = '1') THEN NEXT_STATE<=State_2; ELSIF(IN_1 = '0') THEN NEXT_STATE<=STATE_3; END IF; WHEN STATE_2 => IF(IN_1='0') THEN NEXT_STATE<=STATE_3; END IF; WHEN STATE_3 => IF(In_1= '1') THEN NEXT_STATE <= STATE_2; END IF; WHEN Others => NEXT_STATE<=STATE_1; END CASE; END PROCESS; end Behavioral;