Hi，大家好，我是个新手，有个问题想请教各位大侠我采用了offset做了时序约束，但是时序仿真时没有任何的变化，和没有做约束的一样。不知道哪里出了问题，请各位大侠指教。谢谢
以下是我写得完整的SRAM的读写源代码：
module sram_rw(
addr,
data,
ce_n,
oe_n,
we_n,
lb_n,
ub_n,
clk,
rst_n,
led,
flash_ce,
flash_oe,
flash_we,
sd_cas,
sd_ras,
sd_we
);
input
clk;
input
rst_n;
output
[17:0] addr;
inout
[15:0] data;
output
ce_n;
output
we_n;
output
oe_n;
output
lb_n;
output
ub_n;
output
[2:0] led;
output
flash_ce;
output
flash_oe;
output
flash_we;
output
sd_cas;
output
sd_ras;
output
sd_we;
wire
flash_ce = 1;
wire
flash_oe = 1;
wire
flash_we = 1;
wire
sd_cas = 1;
wire
sd_ras = 1;
wire
sd_we = 1;
reg
[17:0] addr_t;
reg
[15:0] data_t;
reg
[15:0] counter;
reg
[15:0] data_r;
reg
we_n;
reg
lb_n;
reg
ub_n;
reg
[2:0] led;
reg
wr_t_n;
reg
next_sate;
wire
[15:0] data;
assign
data = (!wr_t_n) ? data_t : 16'hzz_zz;
assign
addr = addr_t;
assign
ce_n = 0;
assign
oe_n = 0;
always @(posedge clk)
begin
if(!rst_n)
begin
counter = 0;
wr_t_n = 0;
end
else if(counter == 16'h0f_ff & !next_sate)
begin
counter = 0;
wr_t_n = ~wr_t_n;
end
else if(next_sate)
counter = counter+1;
else counter = counter;
end
always @(posedge clk)
begin
if(!rst_n)
begin
addr_t = 18'h3_ff_ff;
data_t = 0;//是否加延时1ns？
we_n = 0;//是否加延时1ns？
lb_n = 1;//是否加延时1ns？
ub_n = 1;//是否加延时1ns？
next_sate = 0;
end
else if(!wr_t_n & !next_sate)
begin
addr_t = {2'b00,counter};
data_t = counter;//是否加邮?ns？
we_n = wr_t_n;//是否加延时1ns？
lb_n = 0;//是否加延时1ns？
ub_n = 0;//是否加延时1ns？
next_sate = 1;
end
else if(!wr_t_n & next_sate)
begin
lb_n = 1;
ub_n = 1;
data_t = 16'hzz_zz; //是窦友?ns？
next_sate = 0;
end
/*
else if(wr_t_n & !next_sate)
begin
addr_t = {2'b00,counter};
we_n = wr_t_n;
lb_n = 0;//是否加延时1ns？
ub_n = 0;//是否加延时1ns？
next_sate = 1;
end
*/
else if(wr_t_n)
begin
if(!next_sate)
begin
we_n = wr_t_n;
next_sate = 1;
lb_n = 0;//是否加延时4ns？
ub_n = 0;//是否加延时4ns？
addr_t = {2'b00,counter};
end
else
begin
data_r = data;//是否加延时3ns
next_sate = 0;
if(counter == 16'hff_ff)
begin
lb_n = 1;//是否加延时4ns？
ub_n = 1;//是否加延时4ns？
end
else
begin
lb_n = lb_n;//是否加延时4ns？
ub_n = ub_n;//是否加延时4ns？
end
end
//next_sate = 0;
end
else
begin
lb_n = 0;
ub_n = 0;
next_sate = 0;
end
end
always @(posedge clk)
begin
if(!rst_n) led[2:0] = 0;
else begin
if(wr_t_n)
begin
led[1] = 1;
led[2] = 0;
if(data_r == counter - 1)
led[0] = 1;
else led[0] = 0;
end
else
begin
led[0] = 0;
led[1] = 0;
led[2] = 1;
end
end
end
endmodule
以下是我写的时序约束
inst "data<0>" TNM = "data";
inst "data<1>" TNM = "data";
inst "data<2>" TNM = "data";
inst "data<3>" TNM = "data";
inst "data<4>" TNM = "data";
inst "data<5>" TNM = "data";
inst "data<6>" TNM = "data";
inst "data<7>" TNM = "data";
inst "data<8>" TNM = "data";
inst "data<9>" TNM = "data";
inst "data<10>" TNM = "data";
inst "data<11>" TNM = "data";
inst "data<12>" TNM = "data";
inst "data<13>" TNM = "data";
inst "data<14>" TNM = "data";
inst "data<15>" TNM = "data";
timegrp "addr" offset = out 12ns after "clk";
net "lb_n" tnm = "bitsel";
net "ub_n" tnm = "bitsel";
timegrp "bitsel" offset = out 11ns after "clk";
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