
- UID
- 121884
- 性别
- 男
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vhdl程序片段
......
ARCHITECTURE...
...
SIGNAL rdadder:INTEGER RANGE 8 DOWNTO 0;
SIGNAL databuffer:BIT_VECTOR(8 DOWNTO 0);
...
PROCESS(clock)
BEGIN
IF clock'EVENT AND clock='1' THEN
IF reset='1' THEN
rdadder<=0;
databuffer<=(OTHERS=>'0');
...
请问在这里的OTHERS是什么用途? |
ftp://bbsupload:5t6H7n8@210.51.188.157 |
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