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请教大家一个VHDL程序

请教大家一个VHDL程序

Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; package coeffs is type coef_arr is array (0 to 16) of signed (8 downto 0); constant coefs: coef_arr:=( "111111001", "111111011", "000001101", "000010000", "111101101", "111010110", "000010111", "010011010", "011011110", "010011010", "000010111", "111010110", "111101101", "000010000", "000001101", "111111011", "111111001"); end coeffs; Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; use work.coeffs.all; entity fir is port(clk,reset: in std_logic; sample: in signed ( 7 downto 0); result: out signed ( 16 downto 0)); end fir; architecture beh of fir is begin fir_main :process type shift_arr is array (16 downto 0) of signed (7 downto 0); variable tmp,old:signed( 7 downto 0); variable pro:signed (16 downto 0); variable acc:signed (16 downto 0); variable shift:shift_arr; begin reset_loop:loop for i in 0 to 15 loop shift(i):=(others=>'0'); end loop; result<=(others=>'0'); wait until clk'event and clk='1'; if reset='1' then exit reset_loop; end if; main:loop tmp:=sample; pro:=tmp*coefs(0); acc:=pro; for i in 15 downto 0 loop old:=shift(i); pro:=old*coefs(i+1); acc:=acc+pro; shift(i+1):=shift(i); end loop; shift(0):=tmp; result<=acc; wait until clk'event and clk='1'; if reset='1' then exit reset_loop; end if; end loop main; end loop reset_loop; end process; end beh; 这个程序编译后,出现一个错误(%DLS-E-NoSuchAttr,Object kind UnconditionalLoop does not have attribute qSym;in GetAttr(qSym).) 这是什么原因啊 我用的是Max+plus II 10.21
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