我编了这个程序运行的时候老是出同一个错误,不知道那里错了!小妹初次编程请各位高手指点一下吧!
library ieee; use ieee.std_logic_1164.all;
entity ad8109 is port(clk,ce,updata,datain,reset:in std_logic; dataoutut std_logic; out8ut std_logic_vector(7 downto 0)); end ad8109;
architecture struct of ad8109 is component shift32 port(a,clk:in std_logic; yut std_logic); end component; component sp port(d,clk:in std_logic; qut std_logic_vector(7 downto 0)); end component; signal a:std_logic_vector(7 downto 0); signal sw:std_logic; begin process(clk,ce,updata,reset) begin if reset='0' then out8<="00000000"; dataout<='0'; elsif(clk'event and clk='0') then if ce='0'then if updata='1' then u1:shift32 port map (datain,clk,sw); dataout<=sw; elsif updata='0' then u2:sp port map (datain,clk,a); out8<=a; end if; end if; end if; end process; end struct; 出的错误是:
error:terminnation notification:error in d:\anny\ad8109.vhd prevent further processing |