我要发一些在fpga学习中常用的缩略语 缩略语, fpga, 学习

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ABEL Advanced Boolean Expression Language (ABEL) is a high-level language (HDL) and compilation system produced by Data I/O Corporation. ABEL-HDL File The ABEL-HDL (ABL) file is a file written in ABEL Hardware Description Language that contains logic expressed as equations, truth tables, and state machine descriptions. accumulator An accumulator is a register for adding, subtracting, or both. adder An adder is a combinatorial circuit that computes the sum of two or more numbers. architecture Architecture is the common logic structure of a family of programmable integrated circuits. The same architecture can be realized in different manufacturing processes. Examples of Xilinx architectures are the Virtex2 , Virtex2Pro, CoolRunner2, and XC9500 devices. analyze The first step in the synthesis flow. In this stage, the HDL code is checked for syntax errors. annotation Annotation is the insertion of simulation values into the schematic. area constraints Area constraints are created by the user or a process such as synthesis to direct the optimization process that takes place during design implementation. arithmetic equations Arithmetic equations specify the special arithmetic capabilities of the Xilinx CPLDs. Arithmetic Logic Unit (ALU) A logic function that performs arithmetic computations, such as addition, multiplication, and comparison operations. The ALU is one component of the Central Processing Unit (CPU). ASIC Application-specific integrated circuit (ASIC), is a full-custom circuit. In which every mask is defined by the customer or a semi-custom circuit (gate array) where only a few masks are defined. asynchronous debugging Asynchronous debugging is a debugging mode in which you capture data without controlling your system clock. asynchronous logic Asynchronous logic changes independently of clock changes. A signal whose intended function is performed immediately at the point the signal is asserted without regard to a clock. Asynchronous Transfer Mode (ATM) ATM is a method of transmitting voice, data, and video in fixed-size packets over high-speed telecommunications channels. attributes Attributes are instructions placed on symbols or nets in an FPGA or CPLD schematic to indicate their placement, implementation, naming, directionality, or other properties.

back-annotation Back-annotation is the translation of a routed or fitted design to a timing simulation netlist. behavioral design Behavioral design is a technology-independent, text-based design that incorporates high-level functionality and high-level information flow. behavioral design method A behavioral design method defines a circuit in terms of a textual language rather than a schematic of interconnected symbols. behavioral simulation Also known as functional simulation. Behavioral simulation is usually performed on designs that are entered using a hardware definition language (HDL). This type of simulation takes place during the pre-synthesis stage of HDL design. Functional simulation checks that the HDL code describes the desired design behavior. Behavioral simulation is a simulation process that is performed by interpreting the equations that define the design. The equations do not need to be converted to the logic that represents them. binary encoding Binary or maximal encoding is a type of state machine encoding that uses the minimum number of registers to encode the machine. Each register is used to its maximum capability. bit A bit is a binary digit representing 0 or 1. BIT file A BIT file is the same as a bitstream file. See bitstream. BitGen Is a program that produces a bitstream for Xilinx device configuration. BitGen takes a fully routed NCD (Circuit Description) file as its input and produces a configuration bitstream, a binary file with a .bit extension. bitstream A bitstream is a stream of data that contains location information for logic on a device, that is, the placement of Configurable Logic Blocks (CLBs), Input/Output Blocks (IOBs), (TBUFs), pins, and routing elements. The bitstream also includes empty placeholders that are filled with the logical states sent by the device during a readback. Only the memory elements, such as flip-flops, RAMs, and CLB outputs, are mapped to these placeholders, because their contents are likely to change from one state to another. When downloaded to a device, a bitstream configures the logic of a device and programs the device so that the states of that device can be read back. A bitstream file has a .bit extension. block 1. A block is a group of one or more logic functions. 2. A block is a schematic or symbol sheet. There are four types of blocks. A Composite block indicates that the design is hierarchical. A Module block is a symbol with no underlying schematic. A Pin block represents a schematic pin. An Annotate block is a symbol without electrical connectivity that is used only for documentation and graphics. boundary scan Boundary scan is the method used for board-level testing of electronic assemblies. The primary objectives are the testing of chip I/O signals and the interconnections between ICs. It is the method for observing and controlling all new chip I/O signals through a standard interface called a Test Access Port (TAP). The boundary scan architecture includes four dedicated I/O pins for control and is described in IEEE spec 1149.1. buffer A buffer is an element used to increase the current or drive of a weak signal and, consequently, increase the fanout of the signal. A storage element. BUFT A BUFT is a tristate buffer. bus A group of two or more signals that carry closely-associated signals in an electronic design.

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carry logic
An architecture feature of the Xilinx Virtex families. Carry logic is designed to speed-up and reduce the area of counters, adders, incrementers, decrementers, comparators, and subtracters. It is a special interconnect that speeds up the carry path of adders and counters from one CLB to another. This dedicated carry line runs along each column of CLBs as well as the top and bottom CLBs. FPGA Express can synthesize carry logic directly.
clock
A clock is a signal that represents the time that a wave stays at a High or Low state. The rising and falling edges of a clock square wave trigger the activity of the circuits.
clock buffer
A clock buffer is an element used to increase the current or drive of a weak clock signal and consequently increase its fanout.
clock enable
A clock enable is a binary signal that allows or disallows synchronous logic to change with a clock signal. When enabled, this control signal permits a device to be clocked and to become active. There are four different states. The two active High states are CE 0 disabled and CE 1 enabled. The two active Low states are CE 0 enabled and CE 1 disabled.
clock input path
A clock input path starts at either an input of the chip or at the output of a flip-flop, latch, or RAM and ends at any clock pin on a flip-flip or latch enable. The clock input path time is the maximum time required for the signal to arrive at the flip-flop clock input. Clock input paths help to determine system-level design timing.
clock skew
Clock skew is the time differential between 2 or more destination pins in a path.
component
A component is an instantiation or symbol reference from a library of logic elements that can be placed on a schematic.
configuration
Configuration is the process of loading design-specific bitstreams into one or more FPGA devices to define the functional operation of the logical blocks, their interconnections, and the chip I/O. This concept also refers to the configuration of a design directory for a particular design library, such as the Virtex library.
constraints
Constraints are specifications for the implementation process. There are several categories of constraints: routing, timing, area, mapping, and placement constraints. Using attributes, you can force the placement of logic (macros) in CLBs, the location of CLBs on the chip, and the maximum delay between flip-flops. PAR does not attempt to change the location of constrained logic.
constraints file
A constraints file specifies constraints (location and path delay) information in a textual form. An alternate method is to place constraints on a schematic.
CPLD
Complex Programmable Logic Device (CPLD). Is an erasable programmable logic device that can be programmed with a schematic or a behavioral design. CPLDs constitute a type of complex PLD based on EPROM or EEPROM technology. They are characterized by an architecture offering high speed, predictable timing, and simple software. The basic CPLD cell is called a macrocell, which is the CPLD implementation of a CLB. It is composed of AND gate arrays and is surrounded by the interconnect area. CPLDs consume more power than FPGA devices, are based on a different architecture, and are primarily used to support behavioral designs and to implement complex counters, complex state machines, arithmetic operations, wide inputs, and PAL crunchers.
critical path
The critical path is a signal in a section of combinatorial logic that limits the speed of the logic. Storage elements begin and end a critical path, which may include I/O pads.
cross-probing
Interprocess communication between the synthesis or simulation results and the source code from which it originated.

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debugging
Debugging is the process of reading back or probing the states of a configured device to ensure that the device is behaving as expected while in circuit.
decoder
A decoder is a symbol that translates n input lines of binary information into 2n output lines. It is the opposite of an encoder.
Delay Locked Loop (DLL)
A digital circuit used to perform clock management functions on and off-chip.
density
Density is the number of gates on a device.
design implementation
Design implementation in Project Navigator is comprised of running a series of specific programs that result in the creation of a completed design based on user design specifications. The implementation process begins with checking design syntax. Language is then translated and optimized. The design logic is then mapped, placed and route. A BIT file is then created for downloading or debugging your design.
design methodologies
Design methodologies are the techniques used to enter a design, either behavioral or schematic entry.
design specification
The design specification is the top-level of a design used to define its
function. The specifications function is created in terms of behavioral
or structural primitives. The two methods of entering a design are
graphical descriptions (schematics) and textual descriptions (HDL).
Design Rule Check (DRC)
Physical Design Rule Check (DRC) is a series of tests to discover logical and physical errors in the design. Physical DRC is applied to the FPGA Editor and BitGen. Results of the DRC are written into the History toolbar.
device
A device is an integrated circuit or other solid-state circuit formed in semiconducting materials during manufacturing. Each Xilinx architecture family contains specific devices, such as xc4003e and xc5202. A complete Xilinx part number includes architecture (for example, xc4000ex), device (for example, xc4028ex), package (for example, pg299), and speed (for example, -3).
device family
Examples of devices families are Virtex2, Virtex2Pro, Spartan2, and Coolrunner2.
device model
A device model is a VHDL description of the internal and external views of a digital device, including the structure and the communication interface of the device with its environment.
downloading
Downloading is the process of configuring or programming a device by sending bitstream data to the device.

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editor
An editor is a tool that allows you to view or modify an ASCII file. The HDL Editor tool is used for editing in Project Navigator.
effort level
Effort level refers to how hard the implementation process tries to place a design. The effort level settings are.
High, which provides the highest quality placement but requires the longest execution time. Use high effort on designs that do not route or do not meet your performance requirements.
Normal, which is the default effort level. It provides the best trade-off between execution time and high quality placement for most designs.
Low, which provides a lower quality placement but requires the shortest execution time.
external clock
The external clock is the system clock that is used from the target board during synchronous mode debugging. To use an external clock, connect the system clock to the CLKI pin and connect the download cable CLKO pin to the system clock loads.
external pin
A macro pin used to connect the components in an instantiated macro to other components in your design (outside of the macro).
fitting
Fitting is the process of putting logic from your design into physical macrocell locations in the CPLD. Routing is performed automatically, and because of the UIM architecture, all designs are routable.
fitter
The fitter is the software that maps a PLD logic description into the target CPLD.
flash memory
Flash memory is a type of programmable chip that retains data even when the power is turned off.
flat design
A flat design is a design composed of multiple sheets at the top-level schematic.
flattening
Flattening is the process of resolving all of the hierarchy references in a design. If a design contains several instantiations of a logic module, the flattened version of that design will duplicate the logic for each instantiation. A flattened design still contains hierarchical names for instances and nets.
flip-flop
A flip-flop is a simple two-state logic buffer activated by a clock and fed by a single input working in combination with the clock. The states are High and Low. When the clock goes High, the flip-flop works as a buffer as it outputs the value of the D input at the time the clock rises. The value is kept until the next clock cycle (rising clock edge). The output is not affected when the clock goes Low (falling clock edge).
floorplanning
Floorplanning is the process of choosing the best grouping and connectivity of logic in a design. It is also the process of manually placing blocks of logic in an FPGA where the goal is to increase density, routability, or performance.
flow
The flow is an ordered sequence of processes that are executed to produce an implementation of a design.
FPGA
Field Programmable Gate Array (FPGA), is a class of integrated circuits pioneered by Xilinx in which the logic function is defined by the customer using Xilinx development system software after the IC has been manufactured and delivered to the end user. Gate arrays are another type of IC whose logic is defined during the manufacturing process. Xilinx supplies RAM-based FPGA devices. FPGA applications include fast counters, fast pipelined designs, register intensive designs, and battery powered multi-level logic.
functional simulation
Functional simulation is the process of identifying logic errors in your design before it is implemented in a Xilinx device. Because timing information for the design is not available, the simulator tests the logic in the design using unit delays. Functional simulation is usually performed at the early stages of the design process.

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gate
A gate is an integrated circuit composed of several transistors and capable of representing any primitive logic state, such as AND, OR, XOR, or NOT inversion conditions. Gates are also called digital, switching, or logic circuits.
global buffers
Global buffers are low-skew, high-speed buffers that connect to long lines. They do not map logic. There is one BUFGP and one BUFGS in each corner of the chip. Primary buffers must be driven by an IOB. Secondary buffers can be driven by internal logic or IOBs.
global 3-state net (STARTUP.GTS)
A global 3-state net is a net that forces all device outputs to high-impedance state unless boundary scan is enabled and executes an EXTEST instruction.
ground bounce
Ground bounce is the occurrence of voltage spikes on the ground or power levels inside a chip primarily due to current changes in the combined inductance of ground pins, bond wires, and ground metalization. This problem frequently occurs when multiple outputs change state simultaneously.
group
A group is a collection of common signals to form a bus. In the case of a counter, for example, the different signals that produce the actual counter values can be combined to form an alias, or group.
guide file
A guide file is a previously placed and routed NCP file that can be used in a subsequent place and route operation.
guided design
Guided design is the use of a previously implemented version of a file for design mapping, placement, and routing. Guided design allows logic to be modified or added to a design while preserving the layout and performance that have been previously achieved

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HDL
Hardware Description Language. A language that describes circuits in textual code. The two most widely accepted HDLs are VHDL and Verilog.
An HDL, or hardware description language, describes designs in a technology-independent manner using a high level of abstraction. The most common HDLs in use today are Verilog and VHDL.
HDL Editor
Project Navigator's editor for ABEL and VHDL source files. The HDL Editor also provides access to language templates.
hierarchical design
A hierarchical design is a design composed of multiple sheets at different levels of your schematic.
hold time
Hold time is the time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct

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IBUF
An IBUF acts as a protection for the chip, shielding it from eventual current overflows.
IC
Integrated Circuit (IC) is a single piece of silicon on which thousands or millions of transistors are combined. ICs are the major building blocks of modern electronic systems.
IEEE
Institute of Electrical and Electronics Engineers.
IEEE 1164 Standard
The IEEE standard for Verilog HDL supported by Open Verilog International.
IFD
IFD is an IOB flip-flop.
iMPACT
iMPACT enables you to configure your PLD designs using Boundary-Scan, Slave Serial, and Select MAP configuration modes, as well as the MultiPRO Desktop Programmer. You can also generate programming files using iMPACT’s System ACE, PROM Formatter, SVF, and STAPL file generation modes. iMPACT is provided with the Xilinx ISE software.
impedance
Impedance is the sum of all resistance and reactance of a circuit to the flow of alternating current.
implement
The second step in the synthesis flow. In this stage, the analyzed HDL is expanded into gates.
implementation
Implementation is the mapping, placement and routing of a design. A phase in the design process during which the design is placed and routed.
implementation tools
Implementation tools implement a design (macros and logic functions) into FPGA CLB and IOB cells.
incremental design
Incremental design refers to the implementation and verification of a design in stages using guided design.
input pad registers and latches
Input pad registers and latches are D-type registers located in the I/O pad sections of the device. Input pad registers can be used instead of macrocell resources.
instance
An instance is one specific gate or hierarchical element in a design or netlist. The term "symbol" often describes instances in a schematic drawing. Instances are interconnected by pins and nets. Pins are ports through which connections are made from an instance to a net. A design that is flattened to its lowest level constituents is described with primitive instances.
instantiation
Instantiation is the act of placing a symbol that represents a primitive or a macro in a design or netlist.
Intellectual Property (IP)
Ready made intellectual property (IP) cores range in complexity from simple arithmetic operators to complex system-level building blocks such as filters, transformers or memory. Xilinx provides intellectual property cores from the Xilinx CORE Generator tool.
IOB (input/output block)
An IOB is a collection or grouping of basic elements that implement the input and output functions of an FPGA device.
I/O blocks
I/O blocks are the input/output logic of the device containing pin.
drivers, registers and latches, and 3-state control functions.
I/O pads
I/O pads are the input/output pads that interface the design logic with the pins of the device.
ISE
Integrated Synthesis Environment.
iterative design
Iterative design refers to the process of using a guide file to add changed logic to a design that has already been verified for timing. It implements logic that has not been changed using the same FPGA resources as in the guide file, which ensures that the timing on those paths is identical. For logic that has been changed, it uses the normal mapping, placement, and routing process.

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JEDEC
JEDEC is a CPLD file format used for downloading device bitmap information to a device programmer.
Johnson counter
A Johnson counter is a counter implemented with the Johnson style.
JTAG Mode
JTAG Mode is a MultiLINX configuration mode supported by the following MultiLINX device families: Virtex, Spartan2, CoolRunner2, XC9500.

xing80

这个，这个，这个个也太乱了吧，看得我直恶心！