我的一个设计，在VertexII下实现的，稍微改一个无关紧要的地方，和DSP联调的结果差异很大（DSP的软件和硬件平台是被另一个功能一样的用另一种hdl语言写的设计验证过的）。很迷茫。请前辈们指教。
下面是一些报告：
Number of Slices containing only related logic:ffice ffice" /> |
990 |
990 |
100% |
Device Utilization Summary: Number of BUFGMUXs 13 out of 16 81% Number of External IOBs 45 out of 484 9% Number of LOCed IOBs 44 out of 45 97% Number of SLICEs 990 out of 14336 6% Number of TBUFs 445 out of 7168 6% WARNING lace:83 - This design either uses more than 8 clock buffers or has clock buffers locked into primary and secondary sites. Since only one clock buffer output signal from a primary / secondary pair may enter any clock region it is necessary to partition the clock logic being driven by these clocks into different clock regions. It may be possible through Floorplanning all or just part of the logic being driven by the Global clocks to achieve a legal placement for this design................ WARNING:CLK Net:dump[3] may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:CLK Net:dump[0] may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:CLK Net:dump[1] may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:CLK Net:dump[2] may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. | 
