[求助] xilinx ip core 不能仿真的问题！ core, xilinx, 仿真, 求助

dingxq

我生成了个mac filter 滤波器，但是仿真的时候却出现这样的问题：
这就是仿真时所报的错误，下面还有类似的语句，真的是把我折腾没脾气了！

ERROR:HDLParsers:3312 - d:/my_design/pncode/dds/dds.vhd Line 683. Undefined symbol 'LUT4'.
ERROR:HDLParsers:3312 - d:/my_design/pncode/dds/dds.vhd Line 699. Undefined symbol 'FDE'.
ERROR:HDLParsers:3312 - d:/my_design/pncode/dds/dds.vhd Line 744. Undefined symbol 'C_DIST_MEM_V6_0'.
ERROR:HDLParsers:3312 - d:/my_design/pncode/dds/dds.vhd Line 885. Undefined symbol 'C_ADDSUB_V6_0'.
ERROR:HDLParsers:3312 - d:/my_design/pncode/dds/dds.vhd Line 1001. Undefined symbol 'C_REG_FD_V6_0'.
ERROR:HDLParsers:3312 - d:/my_design/pncode/dds/dds.vhd Line 1025. Undefined symbol 'C_SHIFT_FD_V6_0'.
ERROR:HDLParsers:1209 - d:/my_design/pncode/dds/dds.vhd Line 1099. C_ADDSUB_V6_0: Undefined symbol (last report in this block)
ERROR:HDLParsers:1209 - d:/my_design/pncode/dds/dds.vhd Line 1152. C_SHIFT_FD_V6_0: Undefined symbol (last report in this block)
ERROR:HDLParsers:1209 - d:/my_design/pncode/dds/dds.vhd Line 1185. LUT4: Undefined symbol (last report in this block)
ERROR:HDLParsers:1209 - d:/my_design/pncode/dds/dds.vhd Line 1201. FDE: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - d:/my_design/pncode/dds/dds.vhd Line 1385. Undefined symbol 'C_GATE_BIT_V6_0'.
ERROR:HDLParsers:1209 - d:/my_design/pncode/dds/dds.vhd Line 1481. C_GATE_BIT_V6_0: Undefined symbol (last report in this block)
ERROR:HDLParsers:1209 - d:/my_design/pncode/dds/dds.vhd Line 1854. C_REG_FD_V6_0: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - d:/my_design/pncode/dds/dds.vhd Line 1900. Undefined symbol 'C_TWOS_COMP_V6_0'.
ERROR:HDLParsers:3312 - d:/my_design/pncode/dds/dds.vhd Line 1932. Undefined symbol 'C_SHIFT_RAM_V6_0'.

我的系数文件都是正确的，请问该怎么办？ 急等回复，谢谢！

skyeasing

你用的什么仿真器。是ModelsimPE或者 SE么？要编译库的，用complxlib命令。