- UID
- 132190
- 性别
- 男
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VHDL程序中,小弟遇到一个问题! LIBRARY STD; USE STD.STD_LOGIC.ALL; ENTITY counter IS PORT(load,clear,clk: IN T_WLOGIC; data_in: IN INTEGER; data_out: OUT INTEGER); END counter; ARCHITECTURE count_255 OF counter IS .......
我在compiler的时候,提示有错误: Errorine2:File c:\documents and settings\achilles\counter.vhd:library error: primary unit"STD_LOGIC" denoted by prefix "STD" must exist in the library.
如何修正这个错误! 请大虾指教一下!谢谢各位! |
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