如何在用vhdl语言完成的数字时钟中添加星期和时区功能 vhdl, 时区, 时钟, 语言, 数字

raul1984love

由于毕业设计有这样的要求,比较棘手 不知道怎么解决,原先的时钟设计已经差不多了,但老师要求加入更多的功能,麻烦斑竹能帮忙解决下,功能项目希望越多越好,我用的芯片板是ep1k30tc1443.

陈石亮

给你一个verilog的作为参考。
该设计没有考虑大小月及闰年等。仅供参考。
module bit_compare
(
clk,
reset,
time_zone,
second,
minute,
hour,
day,
month,
year,
week_day,
);
input clk;
input reset;
input[4:0] time_zone;//0~23
output[5:0] second;//0~59
output[5:0] minute;//0~59
output[4:0] hour;//0~23
output[4:0] day;//0~30
output[3:0] month;//0~11
output[11:0] year;//0~9999
output[2:0] week_day;//0~6
//----------------------------------------------------

//------------------------------------------------------
//+generate 1ms
//clk=10Mhz
`define MS_VALUE 10000
reg[14:0] ms_counter;
reg ms;
always @ ( posedge clk or posedge reset )
begin
if( reset )
begin
ms<=0;
ms_counter <= `MS_VALUE;
end
else
begin
ms_counter<=ms_counter-1;
if(ms_counter==0)
begin
ms_counter <= `MS_VALUE;
ms <= ~ms;
end
end
end
//-generate 1ms
//------------------------------------------------------

//------------------------------------------------------
//+generate 500ms
//clk=1ms
`define S_VALUE 500
reg[14:0] s_counter;
reg s;
always @ ( posedge ms or posedge reset )
begin
if( reset )
begin
s<=0;
s_counter <= `S_VALUE;
end
else
begin
s_counter<=s_counter-1;
if(s_counter==0)
begin
s_counter <= `S_VALUE;
s <= ~s;
end
end
end
//-generate 500ms
//------------------------------------------------------

//------------------------------------------------------
//clk=s
reg[5:0] second;//0~59
reg[5:0] minute;//0~59
reg[31:0] hours;//0~+00

always @ ( posedge s or posedge reset )
begin
if( reset )
begin
second<=0;
minute<=0;
hours<=8667264;//2006Äê3ÔÂ11ÈÕ0µã //0+11*24+3*30*24+2006*12*30*24=11*24+(3+2006*12)*360=8667264
end
else
begin
second <= second+1;
if(second==59)
begin
second <= 0;
minute <= minute+1;
if(minute==59)
begin
minute <= 0;
hours <= hours+1;
end
end
end
end
//------------------------------------------------------
reg[4:0] hour;//0~23
reg[4:0] day;//0~30
reg[3:0] month;//0~11
reg[11:0] year;//0~9999
reg[2:0] week_day;//0~6

reg[31:0] totel_hours;//0~+00
reg[31:0] totel_days;//0~+00
reg[31:0] totel_months;//0~+00
always @ ( posedge s or posedge reset )
begin
if( reset )
begin
hour<=0;
day<=0;
month<=0;
year<=0;
end
else
begin
totel_hours <= hours+time_zone;

hour <= totel_hours%24;
totel_days <= totel_hours/24;

day <= totel_days%30;
totel_months <= totel_days/30;

month <= totel_months%12;
year<= totel_months/12;

week_day <= totel_days%7;// 0Äê0ÔÂ0ÈÕµÄʱºò£¬ÐÇÆÚÈÕ.
end
end
//------------------------------------------------------
endmodule

raul1984love

谢谢楼上的帮忙 但有点运行不起来  我这个不太懂的

raul1984love

2楼的能不能帮我把程序转为vhdl语言啊!!!

woshizl

sdfdfdf