请教高手：Protel DXP 编译中的提示[warning] 和[error]如何处理？ warning, error, DXP, Protel, 提示

Maywolf

    我现在使用的是经过三次升级的Protel DXP 即已经与 Altium Designer 没有什么区别了。使用中，在编译时遇到了以下的几个提示，不知道改怎么处理？ 请高手指点。

    1.[Warning] main mcu of final3.SCHDOC Compiler Adding items to hidden net GND

    2.[Warning] main mcu of final3.SCHDOC Compiler Adding items to hidden net VCC 

    3.[Warning] top of final3.SCHDOC Compiler Same parameter contains different values top of final3.SCHDOC Undefined and  

    4.[Warning] main mcu of final3.SCHDOC Compiler NetU2_1 contains IO Pin and Unspecified Port objects (Port MAX186 CS) 

    5.[Warning] anolog input of final3.SCHDOC Compiler NetU5_10 contains Input Pin and Unspecified Port objects (Port SHDN) 

    6.[Warning] top of final3.SCHDOC Compiler Same parameter contains different values top of final3.SCHDOC  and 1.0

    7.[Warning] top of final3.SCHDOC Compiler Nets Wire JTAG_TCK has multiple names (Net Label JTAG_TCK,Sheet Entry external expand of final3-N24(Passive)) 

    8.[Warning] anolog input of final3.SCHDOC Compiler Net VOLTAGE 4 has no driving source (Pin R17-1,Pin R20-1,Pin U3-9,Pin U5-5) 

    以上就是我遇到的集中编译错误。不知道这些错误是否会导致PCB网络表的错误，所以，在交付厂家生产PCB板之前，望各位高手不吝赐教。

    再次不胜感激！！！

                                                      Maywolf  

一通百通

1.[Warning] main mcu of final3.SCHDOC Compiler Adding items to hidden net GND

网络***隐藏，原理图上没有***与之相连，改元件。

2.[Warning] main mcu of final3.SCHDOC Compiler Adding items to hidden net VCC

同上

3.[Warning] top of final3.SCHDOC Compiler Same parameter contains different values top of final3.SCHDOC Undefined and

元件上同一个参数含有不同的命名

4.[Warning] main mcu of final3.SCHDOC Compiler NetU2_1 contains IO Pin and Unspecified Port objects (Port MAX186 CS)

端口不匹配

5.[Warning] anolog input of final3.SCHDOC Compiler NetU5_10 contains Input Pin and Unspecified Port objects (Port SHDN)

同上

6.[Warning] top of final3.SCHDOC Compiler Same parameter contains different values top of final3.SCHDOC and 1.0

同上
7.[Warning] top of final3.SCHDOC Compiler Nets Wire JTAG_TCK has multiple names (Net Label JTAG_TCK,Sheet Entry external expand of final3-N24(Passive))


同上
8.[Warning] anolog input of final3.SCHDOC Compiler Net VOLTAGE 4 has no driving source (Pin R17-1,Pin R20-1,Pin U3-9,Pin U5-5)

同上