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lianzishu

在作计算器时，出现下列错误，清高手指点
ERROR:HDLParsers:1215 - "e:/xilinx/project4/computer/bcd_add_sub.vhd" Line 75. Prefix clock is type std_ulogic, which is not a record type but Enumeration
ERROR:HDLParsers:1217 - "e:/xilinx/project4/computer/bcd_add_sub.vhd" Line 75. Symbol clock can't be used as a prefix in a selected name.
ERROR:HDLParsers:1212 - "e:/xilinx/project4/computer/bcd_add_sub.vhd" Line 75. Invalid selected name clock.
ERROR:HDLParsers:3324 - "e:/xilinx/project4/computer/bcd_add_sub.vhd" Line 74. IN mode Formal clock of regne with no default value must be associated with an actual value.
ERROR:HDLParsers:1215 - "e:/xilinx/project4/computer/bcd_add_sub.vhd" Line 78. Prefix clock is type std_ulogic, which is not a record type but Enumeration
ERROR:HDLParsers:1217 - "e:/xilinx/project4/computer/bcd_add_sub.vhd" Line 78. Symbol clock can't be used as a prefix in a selected name.
ERROR:HDLParsers:1212 - "e:/xilinx/project4/computer/bcd_add_sub.vhd" Line 78. Invalid selected name clock.
ERROR:HDLParsers:3324 - "e:/xilinx/project4/computer/bcd_add_sub.vhd" Line 77. IN mode Formal clock of regne with no default value must be associated with an actual value.

 

原码

lianzishu

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.faddpcg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bcd_add_sub is
port(clock,s,ea,eb:in std_logic;
dataa,datab :in std_logic_vector(11 downto 0);
sel :in std_logic;
sum ut std_logic_vector(15 downto 0);
done ut std_logic);
end bcd_add_sub;

architecture Behavior of bcd_add_sub is
type state_type is(s1,s2);
signal y:state_type;
signal ec,lc,z,co,negative_com:std_logic;
signal a,b,sumc:std_logic_vector(11 downto 0);
signal count:integer range 0 to 7;
begin
fsm_transition:process(clock)
begin
if clock'event and clock='1'then
case y is
when s1=>
if z='0'then
y<=s1;
else
y<=s2;
end if;
when s2=>
if s='1'then
y<=s2;
else
y<=s1;
end if;
end case;
end if;
end process;
fsm_output:process(y)
begin
case y is
when s1=>
done<='0';
when s2=>
done<='1';
end case;
end process;

rega:regne generic map(n=>12)
port map(dataa,ea,clock.a);

regb:regne generic map(n=>12)
port map(datab,eb,clock.b);

ec<='1';
lc<=not s;

counter:downcnt generic map(modulus=>8)
port map(clock,ec,lc,count);

z<='1'when count=0 else'0';

bcd:bcd3 port map(a,b,sel,sel,co,sumc);

negative_com<= sel and (not co);

sum(15 downto 13)<="000"when negative_com='0'else "111";
sum(12)<=((not sel)and co);
com:negative port map(sumc,negative_com,sum(11 downto 0));
end Behavior;