| 一个最简单的示例:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter17 is
port(clk:in std_logic;
q:buffer std_logic_vector(16 downto 0)
);
end counter17;
architecture behave of counter17 is
begin
process(clk)
begin
if clk'event and clk='1' then
q<=q+1;
end if;
end process;
end behave;
建议你多看看VHDL的书 |
