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求教

求教

一段小程序,老是仿真出现问题如下:



Launching Application for process "Generate Expected Simulation Results".


Reading C:/Modeltech_5.7/tcl/vsim/pref.tcl


# 5.7


# do bb.ado
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim SE vcom 5.7 Compiler 2002.12 Dec 18 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity i8051_dec
# -- Compiling architecture dfl of i8051_dec
# Model Technology ModelSim SE vlog 5.7 Compiler 2002.12 Dec 18 2002
# -- Compiling module bb
#
# Top level modules:
#  bb
# vsim -lib work -t 1ps bb
# Attempting stack trace sig 11
# Signal caught: signo [11]
# vsim_stacktrace.vstf written
# Current time Thu Apr 13 14:53:23 2006
# ModelSim Stack Trace
# Program = vsim
# Id = "5.7"
# Version = "2002.12"
# Date = "Dec 19 2002"
# Platform = win32
# 0    0x004c6023: '<unknown (@0x4c6023)> + 0x20ff3'
# 1    0x004c5f4e: '<unknown (@0x4c5f4e)> + 0x20f1e'


# Corrupt Call Stack


# Loading work.bb
# Loading C:/Modeltech_5.7/win32/../std.standard
# Loading C:/Modeltech_5.7/win32/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_5.7/win32/../ieee.std_logic_arith(body)
# Loading work.i8051_dec(dfl)
# ** Fatal: (SIGSEGV) Bad pointer access.
#    Time: 0 ps  Iteration: 0  Process: /bb/UUT/line__38 File: ../8051/8051/i8051_dec.vhd
# FATAL ERROR while loading design
# Error loading design
Error loading design
ERROR: VSim failed to simulate annotated testbench


源代码如下:


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;


entity i8051_dec is
    port(
  rst  : in  STD_LOGIC;
         op_in   : in  UNSIGNED (7 downto 0);
         op_out  : out UNSIGNED (8 downto 0));
end i8051_dec;


-------------------------------------------------------------------------------


architecture DFL of i8051_dec is


 
  begin
  process(rst,op_in)
  begin
    if(rst='1') then
  op_out<=("000000000" );
 else
    
        case  op_in is
    when "00010001"=>op_out <=("010000000" ) ;
          when others=>op_out<="111111111" ; 
             -- ("00" & OPC_ERROR ); 
    end case;
    
 end if; 
 end process;       
end DFL;

是不是 我的MODELSIM有问题
多谢 斑主

换了个license就没有问题了
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