library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity flash is
Port ( clk : in std_logic;
rst : in std_logic;
flash_out : out std_logic);
end flash;
architecture Behavioral of flash is
component clock is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of clock: component is true;
--attribute syn_black_box of clock: component is true;
signal temp: std_logic_vector(1 downto 0);
signal derive_clk,inter_clk,ready: std_logic;
signal inter_signal : std_logic;
begin
u1: clock
port map(
CLKIN_IN=> clk,
RST_IN=> rst,
CLK0_OUT=>inter_clk,
LOCKED_OUT=>ready,
CLKIN_IBUFG_OUT=>open);
process(inter_clk)
begin
if(ready='1') then
if(inter_clk'event and inter_clk='1') then
temp<=temp+1;
if(temp="11") then
derive_clk<= not derive_clk;
end if;
end if;
end if;
end process;
process(derive_clk)
begin
if(derive_clk'event and derive_clk='1') then
inter_signal<=not inter_signal;
end if;
end process;
flash_out<= inter_signal;
end Behavioral;
上面是源程序，用了一个IP核：DCM，用synplify综合，输出EDIF文件，用ISE implement，结果出错了。提示：ERROR:NgdBuild:604 - logical block 'u1' with type 'clock' could not be resolved.
A pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'clock' is not supported in target
'spartan3'.
还要在ISE工程中添加什么文件吗，添加core generator生成的clock.xaw也不行，还是提示同样的错误，高手指点啊，到底怎么回事？
[此贴子已经被作者于2006-6-23 13:18:15编辑过] | 
