ChipSync is a technology in every I/O of Virtex-4 and Virtex-5 devices. It helps designers to effectively implement source synchronous interface (e.g DDR2, SPI4) easily. In short, ChipSync includes:
1) Input delay chain in every I/O, so that designers can adjust the delay elements they wanted to insert in each differnt data pin or clock pin
2) A serdes so that it can serialize and deserialize data signals
3) Bit alignment and word alignment
4) Output delay elements, so that designers can easily interface source synchronous signal from FPGA to other chips.
Most importantly, every I/O in Virtex-4 and Virtex-5 device has this capability, so that it gives users the maximize flexibility.
