哪位高人有fifo的VHDL代码阿？实际烧到片子里能运行通过的！
我是新手，在网上看到一些代码，都不太对，需要修改，我自己参考着编了一个，仿真通过，但还是烧到片子里不能运行，无输出，希望哪位高人指点一下！给我一个验证过的完全正确的代码让我参考一下！谢谢了，好长时间都没解决，非常郁闷！
我把我的代码附在这里，同时希望批评指正！
library ieee;
use ieee.std_logic_1164.all;
entity fifo is
port
(
clkwr,clkrd,wr,rd,cs:in std_logic;
din :in std_logic_vector( 0 to 7);
dout  ut std_logic_vector( 0 to 7);
full,empty ut std_logic
);
end fifo;
architecture fifo_arch of fifo is
type memory is array (0 to 3) of std_logic_vector( 0 to 7);
signal ram:memory;
signal wp: integer range 0 to 7 :=0;
signal rp: integer range 0 to 7 :=0;
signal in_full,in_empty:std_logic;
begin
process(clkwr,cs) -----------------------------------------write
begin
if rising_edge(clkwr) and cs='0' then
if (wr='0' and in_full='0') then
ram(wp)<=din;
end if;
end if;
end process;
process(clkrd) -----------------------------------------read
begin
if rising_edge(clkrd) and cs='0' then
if (rd='0' and in_empty='0') then
dout<=ram(rp);
else
dout<="ZZZZZZZZ";
end if;
end if;
end process;
process(clkwr) -----------------------------------------write hand
begin
if rising_edge(clkwr) and cs='0' then
if (wr='0' and in_full='0') then
if(wp=3) then
wp<=0;
else wp<=wp+1;
end if;
end if;
end if;
end process;
process(clkrd) ------------------------------------------------read hand
begin
if rising_edge(clkrd) and cs='0' then
if (rd='0' and in_empty='0') then
if(rp=3) then
rp<=0;
else rp<=rp+1;
end if;
end if;
end if;
end process;
process(clkrd) -------------------------------------------------empty
begin
if falling_edge(clkrd) and cs='0' then
if ((wp=rp) or (wp=rp+1) or ((wp=0) and (rp=3)))then
in_empty<='1';
else
in_empty<='0';
end if;
end if;
end process;
process(clkwr) --------------------------------------------------full
begin
if falling_edge(clkwr) and cs='0' then
if ((rp=wp+1)or ((wp=3) and (rp=0))) then
in_full<='1';
else
in_full<='0';
end if;
end if;
end process;
full<=in_full;
empty<=in_empty;
end fifo_arch;
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