This error can occur for several reasons:
- Using ModelSim XE with a user-compiled SimPrim Library
- Using ModelSim XE/PE/SE and applying the SDF to an RTL (pre-synthesis) design
Using ModelSim XE with a User-compiled SimPrim Library
All of the Xilinx libraries are pre-compiled and installed with MXE. It is required that the pre-compiled libraries are used with MXE. If you have manually compiled the simulation libraries, you must re-install MXE or download the latest pre-compiled libraries from the Web and install them.
For information on obtaining the updated pre-compiled libraries, see (Xilinx Answer 10616).
Using ModelSim XE/PE/SE and Applying the SDF to an RTL (pre-synthesis) Design
The SDF file contains delay information for all the gates and wires in the netlist. However, for the simulator to account for those delays, the gate-level (structural/back-annotated) netlist that is written by the Xilinx netlister tools (NGD2VHDL/NGD2VER) must be used. If the SDF is used with an RTL design file, this error will occur.
Usually, this error is due to the Xilinx netlister tools renaming the top-level entity name when the "-te" option is used ("-tm" option for Verilog). (By default, the Xilinx netlister tools retain the top-level entity name as it appeared in the RTL design.)
There are two resolutions to this problem:
- Check the top-level entity/module name in the output VHDL/Verilog file generated by Xilinx, and change the instantiation in the test bench to match it.
- Ensure that the "-te" option ("-tm" for Verilog) is not used.
