| 我的程序在MAXPLUS2中编译无法通过，请问问题出在哪里
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity seq_gen is
port(clk_seq : in std_logic;
rst_seq : in std_logic;
lcd_hs_out : out std_logic;--行同步信号HS
lcd_dataen : out std_logic;
lcd_vs_out : out std_logic;--场同步信号VS
pix_clk : out std_logic );
end seq_gen;
architecture rtl_seq_gen of seq_gen is
signal lcd_hb : std_logic;--行消隐信号HB
signal lcd_hs : std_logic;--行同步信号HS
signal lcd_vb : std_logic;--场消隐信号VB
signal lcd_vs : std_logic;--场同步信号VS
signal clken_vcount : std_logic;
begin
hcount: block
signal hcountreg :std_logic_vector(9 downto 0);
signal hz_temp : std_logic;
signal lcd_hz : std_logic;
begin
process (clk_seq,lcd_hz)
begin
if (lcd_hz = '1') then
hcountreg <= (others =>'0');
elsif clk_seq'event AND clk_seq = '1' then
hcountreg <=hcountreg +1;
end if;
end process;
lcd_hb <= '0' when hcountreg >=750 AND hcountreg < 800 --650/800(现在) 615/525（现在）替换
else '1';
lcd_hs <='0' when hcountreg >=520 AND hcountreg < 530
else '1';
hz_temp <= '1' when hcountreg = 800 else '0';
lcd_hz <=hz_temp or rst_seq;
end block hcount;
diff : block
signal inputrega : std_logic;
signal inputregb : std_logic;
begin
process(clk_seq)
begin
if clk_seq'event AND clk_seq='1' then
inputregb <= inputrega;
inputrega <= not lcd_hs;
end if;
end process;
clken_vcount <= not inputregb and inputrega;
end block diff;
vcount : block
signal vcountreg : std_logic_vector(9 downto 0);
signal vz_temp : std_logic;
signal lcd_vz : std_logic;
begin
process (clk_seq,lcd_vz)
begin
if(lcd_vz='1')then
vcountreg <= (others => '0');
elsif clk_seq'event and clk_seq = '1' then
if clken_vcount = '1' then
vcountreg <= vcountreg +1;
end if;
end if;
end process;
lcd_vb <= '0' when vcountreg >=780 and vcountreg < 800
else '1';
lcd_vs <='0' when vcountreg >=520 and vcountreg < 525
else '1';
vz_temp <= '1' when vcountreg = 800 else '0';
lcd_vz <= vz_temp or rst_seq;
end block vcount;
pix_clk <=clk_seq;
lcd_dataen <=lcd_hb and lcd_vb;
lcd_hs_out <=lcd_hs;
lcd_vs_out <=lcd_vs;
end rtl_seq_gen; |
