写了个模块 ,调试时总是读不出来值,请大家知道下,鉴别下哪里出错了. module counter(
reset_n,
clk_av,
io, s_address,
s_chipselect,
s_read_n,
s_write_n,
s_writedata,
s_readdata
);
input reset_n;
input clk_av;
input io;
input [15:0] s_address;
input s_chipselect;
input s_read_n;
input s_write_n;
input [15:0] s_writedata;
output [15:0] s_readdata; reg [15:0] s_readdata;
reg [15:0] counter_reg;
reg [15:0] counter;
reg [15:0] start_reg;
reg [15:0] end_reg; always@(posedge clk_av or negedge reset_n)
begin
counter_reg <= counter;
if(~reset_n)
counter_reg <= 16'd0;
else if(s_chipselect &(~s_write_n)&(s_address == 16'd0))
counter_reg <= s_writedata;
end always@(posedge clk_av or negedge reset_n)
begin
if(~reset_n)
start_reg <= 16'd0;
else if(s_chipselect &(~s_write_n)&(s_address == 16'd1))
start_reg <= s_writedata;
end always@(posedge clk_av or negedge reset_n)
begin
if(~reset_n)
s_readdata <= 16'd0;
else if(s_chipselect &(~s_read_n))
begin
case(s_address)
16'd0:
s_readdata <= counter_reg; //16'h00ff;//
16'd1:
s_readdata <= start_reg;
default:
s_readdata <= 16'dz;
endcase
end
end
always@(io)
begin
if(start_reg==16'd1)
counter <= counter + 1;
end
endmodule | 
