ADI ADSP－21489 SHARC处理器开发方案

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我是MT发表于 2014-3-6 20:49 | 只看该作者

ADI ADSP－21489 SHARC处理器开发方案

处理器, 开发

关键词： ADI , ADSP－21489 , SHARC , 处理器

ADI公司的ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488和ADSP-21489是第四代SHARC®处理器,基于单指令多数据(SIMD)核,支持32位定点和32/40位浮点算法格式,具有400 MHz/2400 MFLOP,提高了性能,基于硬件的滤波器加速器,音频性能和集中于应用的确外设,支持最新环绕声译码器算法的新存储器配置.主要用于工业控制,汽车音频和医疗电子.本文介绍了ADSP-2148x系列产品主要特性,方框图,以及评估板ADSP-21489 EZ-KIT Lite®主要特性,框图,电路图和材料清单.

The SHARC ADSP-21489 is one of two new members of the fourth generation of SHARC® Processors, that now includes the ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.

The ADSP-21489 offers the highest performance – 400 MHz/2400 MFLOPs – in an LQFP package within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21489 particularly well suited to address the automotive audio and industrial control segments. In addition to its high core performance, the ADSP-21489 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.

Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, IDP, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as SPI,UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

ADSP-2148x系列产品性能总结表:

ADSP-2148x主要特性:

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip

ROM

Up to 400 MHz operating frequency

Code compatible with all other members of the SHARC family

The ADSP-2148x processors are available with unique audiocentric

peripherals, such as the digital applications

interface, serial ports, precision clock generators, S/PDIF

transceiver, asynchronous sample rate converters, input

data port, and more

ADSP-2148x系列产品应用:

Industrial Control

Automotive Audio

Medical Applications

图1.ADSP-2148x系列产品方框图

评估板ADSP-21489 EZ-KIT Lite®

The ADSP-21489 EZ-KIT Lite® provides developers with a cost-effective method for initial evaluation of the ADSP-21483/21486/21487/21489 SHARCs® Processors via a USB-based, PC-hosted tool set. With this EZ-KIT Lite, users can learn more about the Analog Devices (ADI) ADSP-21489 hardware and software development, and quickly prototype a wide range of applications.

The EZ-KIT Lite includes an ADSP-21489 SHARC Processor desktop evaluation board along with an evaluation suite of the VisualDSP++® development and debugging environment, including the C/C++ compiler, assembler, and linker. The evaluation suite of VisualDSP++ is designed to be used with the EZ-KIT Lite only.

The EZ-KIT Lite also comes with a standalone debug agent board that is removable to allow a user to plug-in an external emulator.

SHARC 21489-EZ-Kit Lite

图2.评估板ADSP-21489 EZ-KIT Lite外形图

评估板ADSP-21489 EZ-KIT Lite主要特性:

• Analog Devices ADSP-21489 SHARC processor

• Core performance up to 400 MHz

• 176-pin LQFP package

• 25MHz CLKIN oscillator

• 5 Mb of internal RAM memory

• Parallel flash memory

• Numonyx M29W320EB – 4 MB (4M x 8 bits)

• SDRAM memory

• Micron MT48LC16M16A2P-6A – 16 Mbx x 16 bits (256 Mb or 32 MB)

• Asynchronous memory (SRAM)

• ISSI IS61WV102416BLL-10TLI – 1M x 16 bits (2 MB)

• SPI flash memory

• Numonyx M25P16 – 16 Mb

• Analog audio interface

• Analog Devices AD1939 audio codec

• 4 x 2 RCA phono jack for eight channels of stereo output

• 4 x 1 RCA phono jack for four channel of stereo input

• Two DB25 connectors for differential inputs/outputs

• 3.5 mm headphone jack with volume control connected to one of the stereo outputs

• Supports all eight DACs and four ADCs in TDM and I2S modes at 48 KHz, 96 KHz, and 192 KHz sample rates

• Digital audio interface (S/PDIF)

• RCA phono jack output

• RCA phono jack input

• Temperature monitor

• ON Semiconductor ADM1032

• Local and remote temperature sensing

• Universal asynchronous receiver/transmitter (UART)

• ADM3202 RS-232 line driver/receiver

• DB9 female connector

• LEDs

• Eleven LEDs: one board reset (red), eight general-purpose (amber), one temperature sensor (amber), and one power (green)

• Push buttons

• Five push buttons: one reset, two connected to the DAI,and two connected to FLAG pins of the processor

• Expansion interface II

• Next generation of the expansion interface design, provides access to most of the processor signals

• Power supply

• 5V @ 3.6 Amps

• Other features

• Watch dog timer (WDT) system reset implementation

• SHARC power measurement jumpers

• JTAG ICE 14-pin header

• USB cable