交织器的一种VHDL实现方法 VHDL

xjuhui

     本人在校大学生，下面是我自己想出的一个实现方法，但是觉得太复杂了，且资源消耗太大。有没有做过这方面的朋友，指导一下，不胜感激。[

library ieee;
use ieee.std_logic_1164.all;
entity interleave is
  port(din:in std_logic;
        clk:in std_logic;
         qoutut std_logic);
 end interleave;
architecture behav of interleave is
 signal count:integer range 0 to 31;
 signal a:std_logic_vector(0 to 15);
 signal b:std_logic_vector(0 to 15);
begin
 process(clk)
begin
 if clk'event and clk='1' then
   if count=7 then
      count<=0;
    else
      count<=count+1;
   end if;
end if;
end process;
process(clk,din,count)
begin
 if clk'event and clk='1' then
   case count is
   when 0 =>a(0)<=din;qout<=b(0);
   when 1 =>a(1)<=din;qout<=b(4);
   when 2 =>a(2)<=din;qout<=b(8);
   when 3 =>a(3)<=din;qout<=b(12);
   when 4 =>a(4)<=din;qout<=b(1);
   when 5 =>a(5)<=din;qout<=b(5);
   when 6 =>a(6)<=din;qout<=b(9);
   when 7 =>a(7)<=din;qout<=b(13);
   when 8 =>a(8)<=din;qout<=b(2);
   when 9 =>a(9)<=din;qout<=b(6);
   when 10 =>a(10)<=din;qout<=b(10);
   when 11 =>a(11)<=din;qout<=b(14);
   when 12 =>a(12)<=din;qout<=b(3);
   when 13 =>a(13)<=din;qout<=b(7);
   when 14 =>a(14)<=din;qout<=b(11);
   when 15 =>a(15)<=din;qout<=b(15);
   when 16 =>b(0)<=din;qout<=a(0);
   when 17 =>b(1)<=din;qout<=a(4);
   when 18 =>b(2)<=din;qout<=a(8);
   when 19 =>b(3)<=din;qout<=a(12);
   when 20 =>b(4)<=din;qout<=a(1);
   when 21 =>b(5)<=din;qout<=a(5);
   when 22 =>b(6)<=din;qout<=a(9);
   when 23 =>b(7)<=din;qout<=a(13);
   when 24 =>b(8)<=din;qout<=a(2);
   when 25 =>b(9)<=din;qout<=a(6);
   when 26 =>b(10)<=din;qout<=a(10);
   when 27 =>b(11)<=din;qout<=a(14);
   when 28 =>b(12)<=din;qout<=a(3);
   when 29 =>b(13)<=din;qout<=a(7);
   when 30 =>b(14)<=din;qout<=a(11);
   when 31 =>b(15)<=din;qout<=a(15);
  end case;
end if;
end process;
 end behav;

一切从零开始

朋友，首先问一下，你仿真结果对吗？你的count是32次循环的，为什么到8就循环呢？

我不大懂交织器，但我看了一下很像fft得到位序地址生成，下面是我编的，你看看对你有没有用，

begin
process(clk)
variable a,b:std_logic_vector(15 downto 0);
variable count:std_logic_vector(3 downto 0);
variable c,ca:integer range 0 to 15;
begin
 if(clk'event and clk='1')then
  ca:=conv_integer(count);
  c:=conv_integer(count(0)&count(1)&count(2)&count(3));
  qout<=b(c);
  a(ca):=din;
  case count is
   when "1111"=>
       b:=a;
      count:="0000";
   when others=>count:=count+1;
  end case;
 end if;
end process;

一共用了55个逻辑们，你看看能不能在优化一下吧

[em08][em08][em08][em08][em08]

xjuhui

非常感谢指点。

这个交织器是这样的：将16个数据按行写入一个4*4的矩阵，然后按列读出。我开始用的是2X2交织器,后来改成4X4，但忘了把count改回来（应该改为31），