《Xilinx可编程逻辑器件设计与开发（基础篇）》连载2：目录 高等院校, 通信工程, 计算机, 源代码, 控制器

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《Xilinx可编程逻辑器件设计与开发（基础篇）》介绍了Xilinx主流FPGA的结构与特点、Xilinx FPGA的开发流程及其常用相关开发工具(包括IP核生成器、FPGA Editor、RTL/Architecture原理图查看器、ChipScope、PlanAhead等工具)的应用，还介绍了业界使用最广泛的仿真工具ModelSim，最后介绍了Xilinx的8位微控制器PicoBlaze。本书配有1张光盘，其中收录了本书所涉及的参考?料、完整工程、源代码等。本书可作为高等院校通信工程、电子工程、计算机、自动化、微电子与半导体等专业的参考书，也可作为硬件工程师、IC设计者的实用工具书。目录第1章 Spartan-3系列FPGA ..........................................................................11.1 Spartan-3 系列内部结构 ...................................................................................................... 21.1.1 可配置逻辑模块（CLB） ............................................................................................. 21.1.2 时钟资源 ........................................................................................................................ 71.1.3 数字时钟管理器（DCM）.......................................................................................... 101.1.4 BRAM（Block RAM）模块 ....................................................................................... 131.1.5 嵌入式硬核乘法器 ....................................................................................................... 141.1.6 IOB模块 ....................................................................................................................... 151.2 Spartan-3型FPGA .............................................................................................................. 181.3 Spartan-3E型FPGA ........................................................................................................... 191.4 扩展Spartan-3A型FPGA .................................................................................................. 191.5 小结 .................................................................................................................................... 21第2章 Spartan-6系列FPGA ........................................................................ 222.1 Spartan-6系列内部模块 ..................................................................................................... 232.1.1 可配置逻辑模块（CLB） ........................................................................................... 232.1.2 时钟资源 ...................................................................................................................... 272.1.3 时钟管理器（CMT） .................................................................................................. 332.1.4 BRAM（Block RAM）模块 ....................................................................................... 412.1.5 DSP模块XtremeDSP .................................................................................................. 442.1.6 SelectIO资源................................................................................................................ 472.1.7 MCB模块 ..................................................................................................................... 562.1.8 GTP模块 ...................................................................................................................... 562.1.9 PCIe端点模块 .............................................................................................................. 572.2 Spartan-6 LX/LXT型FPGA ............................................................................................... 582.3 小结 .................................................................................................................................... 58第3章 Virtex-4系列FPGA ........................................................................... 593.1 ASMBL架构 ....................................................................................................................... 603.2 Virtex-4内部模块 ............................................................................................................... 613.2.1 可配置逻辑模块（CLB） ........................................................................................... 613.2.2 时钟资源 ...................................................................................................................... 663.2.3 数字时钟管理器（DCM）.......................................................................................... 703.2.4 相位匹配时钟分频器（PMCD） ............................................................................... 713.2.5 BRAM（Block RAM）模块 ....................................................................................... 723.2.6 DSP模块XtremeDSP .................................................................................................. 7423.2.7 SelectIO模块................................................................................................................ 783.2.8 RocketIO模块 .............................................................................................................. 863.2.9 以太网（Ethernet MAC）模块 ................................................................................... 883.2.10 处理器核（PowerPC405） ........................................................................................ 913.3 Virtex-4 LX型FPGA .......................................................................................................... 923.4 Virtex-4 SX型FPGA .......................................................................................................... 923.5 Virtex-4 FX型FPGA .......................................................................................................... 933.6 小结 .................................................................................................................................... 94第4章 Virtex-5系列FPGA ........................................................................... 954.1 Virtex-5系列器件内部逻辑结构 ....................................................................................... 974.1.1 可配置逻辑模块（CLB） ........................................................................................... 974.1.2 时钟资源 .................................................................................................................... 1024.1.3 Select IO技术 ............................................................................................................. 1084.1.4 Rocket I/O技术 .......................................................................................................... 1144.1.5 嵌入式DSP模块 ....................................................................................................... 1154.1.6 嵌入式PCIe模块 ....................................................................................................... 1174.1.7 嵌入式PowerPC模块 ............................................................................................... 1184.2 Virtex-5 LX ........................................................................................................................ 1194.3 Virtex-5 LXT ..................................................................................................................... 1204.4 Virtex-5 SXT ...................................................................................................................... 1204.5 Virtex-5 TXT ..................................................................................................................... 1214.6 Virtex-5 FXT ...................................................................................................................... 1224.7 小结 .................................................................................................................................. 123第5章 Virtex-6系列FPGA ......................................................................... 1245.1 Virtex-6内部模块 ............................................................................................................. 1255.1.1 可配置逻辑模块（CLB） ......................................................................................... 1255.1.2 时钟资源 .................................................................................................................... 1305.1.3 混合模式时钟管理器（MMCM） ........................................................................... 1355.1.4 BRAM（Block RAM）模块 ..................................................................................... 1395.1.5 DSP模块XtremeDSP ................................................................................................ 1405.1.6 SelectIO模块.............................................................................................................. 1465.1.7 GTX模块 ................................................................................................................... 1525.1.8 GTH模块 ................................................................................................................... 1555.1.9 以太网（Ethernet MAC）模块 ................................................................................. 1555.1.10 PCIe端点模块 .......................................................................................................... 1585.2 Virtex-6 LXT型FPGA ..................................................................................................... 1585.3 Virtex-6 SXT型FPGA ..................................................................................................... 15935.4 Virtex-6 HXT型FPGA ..................................................................................................... 1595.5 小结 .................................................................................................................................. 161第6章 Xilinx ISE 11.x开发流程 .................................................................. 1626.1 设计输入 ........................................................................................................................... 1636.1.1 设计要求 .................................................................................................................... 1636.1.2 认识ISE软件界面 ..................................................................................................... 1686.1.3 创建工程 .................................................................................................................... 1696.2 添加约束 ........................................................................................................................... 1726.2.1 引脚约束 .................................................................................................................... 1736.2.2 时序约束 .................................................................................................................... 1766.3 XST综合 ........................................................................................................................... 1826.3.1 XST综合属性设置 .................................................................................................... 1826.3.2 XST综合流程 ............................................................................................................ 1906.4 实现 .................................................................................................................................. 1926.4.1 翻译阶段 .................................................................................................................... 1936.4.2 映射阶段 .................................................................................................................... 1956.4.3 布局布线阶段............................................................................................................. 1996.5 ISim仿真 ........................................................................................................................... 2026.5.1 添加仿真文件............................................................................................................. 2026.5.2 行为仿真 .................................................................................................................... 2036.5.3 时序仿真 .................................................................................................................... 2036.6 iMPACT编程与配置 ........................................................................................................ 2046.6.1 使用iMPACT生成FPGA配置文件 ........................................................................ 2046.6.2 使用iMPACT生成PROM编程文件 ....................................................................... 2046.6.3 使用iMPACT配置/编程 ........................................................................................... 2076.7 小结 .................................................................................................................................. 209第7章 ISE 11.x的辅助设计工具 ................................................................. 2107.1 IP核生成工具和结构化设计向导 ................................................................................... 2107.1.1 用Core Generator建立一个工程 .............................................................................. 2127.1.2 用Core Generator生成存储器 .................................................................................. 2167.1.3 用Core Generator生成时钟管理单元 ...................................................................... 2247.2 FPGA底层编辑器（FPGA Editor） ............................................................................... 2417.2.1 认识FPGA Editor底层编辑器 .................................................................................. 2427.2.2 FPGA底层编辑器设计实例 ..................................................................................... 2457.3 RTL寄存器传输级原理图查看器 ................................................................................... 2517.3.1 RTL寄存器传输级原理图查看器的使用 ................................................................ 2517.3.2 RTL寄存器传输级原理图查看器的使用技巧......................................................... 25647.4 Technology门级原理图查看器 ........................................................................................ 2587.4.1 利用Technology原理图查看器进行层次分析 ........................................................ 2587.4.2 利用Technology原理图辅助时序分析 .................................................................... 2627.5 小结 .................................................................................................................................. 265第8章 编程与配置....................................................................................... 2668.1 Xilinx FPGA的配置模式 ................................................................................................. 2668.1.1 主动串行模式............................................................................................................. 2678.1.2 被动串行模式............................................................................................................. 2708.1.3 主动并行模式............................................................................................................. 2718.1.4 被动并行模式............................................................................................................. 2728.1.5 边界扫描模式............................................................................................................. 2758.1.6 高级配置模式──SPI ............................................................................................... 2778.1.7 高级配置模式──BPI .............................................................................................. 2818.1.8 高级配置模式──System ACE ................................................................................ 2838.2 Xilinx FPGA器件的配置流程 ......................................................................................... 2838.3 Xilinx FPGA器件配置的硬件方案 ................................................................................. 2858.4 Xilinx器件的配置文件 .................................................................................................... 2878.5 iMPACT软件简介 ............................................................................................................ 2908.6 小结 .................................................................................................................................. 296第9章 ChipScope Pro调试设计 ................................................................. 2979.1 ChipScope Pro相关IP核 ................................................................................................. 2999.2 ChipScope Pro核生成器 .................................................................................................. 3029.2.1 ICON属性 .................................................................................................................. 3039.2.2 ILA属性 ..................................................................................................................... 3049.2.3 VIO属性 .................................................................................................................... 3079.2.4 ATC2属性 .................................................................................................................. 3089.2.5 ChipScope Pro内核生成器应用实例 ........................................................................ 3119.3 ChipScope Pro内核插入器 .............................................................................................. 3189.4 ChipScope Pro分析仪 ...................................................................................................... 3289.5 利用FPGA Editor修改Chipscope Pro核信号连接 ....................................................... 3359.6 小结 .................................................................................................................................. 336第10章 PlanAhead工具应用 ...................................................................... 33710.1 PlanAhead开发流程 ....................................................................................................... 33710.2 PlanAhead输入、输出文件 ........................................................................................... 33810.3 用PlanAhead进行RTL代码开发与分析 ..................................................................... 34010.4 应用PlanAhead进行I/O规划 ....................................................................................... 354510.5 PlanAhead与时序分析 ................................................................................................... 36310.6 应用PlanAhead进行布局规划 ...................................................................................... 36810.7 PlanAhead与ChipScope ................................................................................................ 37210.8 PlanAhead导入导出功能 ............................................................................................... 38010.9 小结 ................................................................................................................................ 380第11章 第三方仿真工具ModelSim ............................................................. 38111.1 ISE 11.x支持的仿真工具 ............................................................................................... 38211.2 ModelSim仿真库的建立 ................................................................................................ 38211.3 认识ModelSim常用窗口 ............................................................................................... 38711.4 ModelSim功能仿真 ........................................................................................................ 39411.4.1 基于Verilog的功能仿真 ......................................................................................... 39411.4.2 基于VHDL的功能仿真 .......................................................................................... 39511.4.3 基本功能仿真流程 ................................................................................................... 39511.4.4 ModelSim的项目管理 ............................................................................................. 40011.4.5 自定义仿真库 ........................................................................................................... 40311.5 ModelSim时序仿真 ........................................................................................................ 40511.5.1 基于Verilog的时序仿真 ......................................................................................... 40511.5.2 基于VHDL的时序仿真 .......................................................................................... 40611.5.3 基本时序仿真流程 ................................................................................................... 40711.5.4 SDF时序标注文件 .................................................................................................. 40911.6 ModelSim波形编辑器与仿真 ........................................................................................ 41011.6.1 用波形编辑器创建激励的步骤 ............................................................................... 41011.6.2 VCD文件 ................................................................................................................. 41211.7 用命令行方式进行仿真 .................................................................................................. 41411.7.1 常用命令介绍 ........................................................................................................... 41411.7.2 命令行仿真实例 ....................................................................................................... 41611.7.3 ModelSim中的do文件 ........................................................................................... 41611.8 ISE与ModelSim协同仿真 ............................................................................................ 41711.9 ModelSim仿真存储器 .................................................................................................... 42011.10 VHDL/Verilog混合仿真 ............................................................................................... 42511.11 仿真结果的存储 ............................................................................................................ 42611.12 小结 ............................................................................................................................... 428第12章 PicoBlaze 8位微控制器 ................................................................. 43012.1 PicoBlaze特性 ................................................................................................................ 43012.2 PicoBlaze硬件基本结构 ................................................................................................ 43112.2.1 PicoBlaze功能模块说明 ......................................................................................... 43112.2.2 PicoBlaze接口信号 ................................................................................................. 432612.2.3 PicoBlaze指令集 ..................................................................................................... 43312.2.4 PicoBlaze中断 ......................................................................................................... 43712.2.5 PicoBlaze Scratchpad RAM──暂存器 .................................................................. 43812.2.6 PicoBlaze输入/输出端口 ........................................................................................ 44012.2.7 PicoBlaze指令存储器配置方式 ............................................................................. 44312.3 PicoBlaze性能 ................................................................................................................ 44512.4 PicoBlaze在FPGA设计中的应用 ................................................................................ 44512.5 PicoBlaze开发工具 ........................................................................................................ 44712.5.1 KCPSM3开发工具 .................................................................................................. 44712.5.2 Mediatronix pBlazIDE开发工具 ............................................................................. 44812.6 PicoBlaze设计开发包 .................................................................................................... 45012.7 PicoBlaze设计实例 ........................................................................................................ 45112.8 小结 ................................................................................................................................ 458