如何在ISE中更新老版本的IP核 selected, version, manager, upgrade, recent

pengpengpang

今天在ISE中打开以前做的一个工程时，总是不停地提示
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the selected IP Block_Memory_Generator v3.1 to a more recent version.
老版本是ISE11.1中生成的，现在用12.4了，推荐更新IP核。于是摸索了一下，找到了下面的步骤：
1.        在导航窗口中选择IP核生成的文件
2.        在core generator中双击manager core，如图所示

3.        点击出现的xilinx core generator窗口中，Actions下面的Update and regenerate……那一项即可，然后会出现提示：
Welcome to Xilinx CORE Generator.
Help system initialized.
Opening project file D:\dul_ram\ipcore_dir\coregen.cgp.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the selected IP Block_Memory_Generator v3.1 to a more recent version.
Project, 'coregen', initialised from file 'D:\dul_ram\ipcore_dir\coregen.cgp'.
Upgrade and regenerate all project IP (latest versions, under current project settings)
Applying current project options...
Finished applying current project options.
Applying current project options...
Finished applying current project options.
Upgrading IP dul_ram to Block Memory Generator version 4.3
Launching upgrade viewer...
Launched upgrade viewer.
Initializing IP model...
Finished initialising IP model.
Generating IP...
WARNING:sim:89 - A core named already exists in the output directory. Output products for this core may be overwritten.
Initializing IP model...
WARNING:sim:602 - The parameter 'Port_B_Write_Rate' is disabled and can't be set to any other value than '0'. Its value will be reset from '50' to its last valid value '0'.
WARNING:sim:192 - Xco Parameter changed from (Port_B_Write_Rate,50) to (Port_B_Write_Rate,0) during Recustomization.
Finished initialising IP model.
XST: HDL Compilation
XST: Design Hierarchy Analysis
XST: HDL Analysis
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
Generating Implementation files.
Generating ISE symbol file...
WARNING:coreutil - WARNING: Default charset GBK not supported, using ISO-8859-1 instead
Generating NGC file.
Finished Generation Stage.
Generating IP instantiation template...
VHDL instantiation template already present, so not regenerating.
WARNING:coreutil - WARNING: Default charset GBK not supported, using ISO-8859-1 instead
Finished generating IP instantiation template.
Generating metadata file...
Finished generating metadata file.
Generating ISE file...
Finished ISE file generation.
Generating FLIST file...
Finished FLIST file generation.
Preparing output directory...
Finished preparing output directory.
INFO:sim - Created backup directory D:\dul_ram\ipcore_dir\tmp\backup_dul_ram\
Moving files to output directory...
Finished moving files to output directory
Saved options for project 'coregen'.