Net fpga_0_Hard_Ethernet_MAC_PHY_MII_INT LOC=H20;
##为fpga_0_Hard_Ethernet_MAC_PHY_MII_INT指定一个电平标准LVCMOS25
Net fpga_0_Hard_Ethernet_MAC_PHY_MII_INT IOSTANDARD = LVCMOS25;
#TIG(Timing IGnore)是忽略fpga_0_Hard_Ethernet_MAC_PHY_MII_INT上的时序问题
Net fpga_0_Hard_Ethernet_MAC_PHY_MII_INT TIG;
##定义sys_clk_pin驱动的所有同步元件为sys_clk_pin的分组
Net sys_clk_pin TNM_NET = sys_clk_pin;
##将sys_clk_pin信号分配到FPGA的AH15管脚上
Net sys_clk_pin LOC = AH15;
##为sys_clk_pin指定一个电平标准LVCMOS33
Net sys_clk_pin IOSTANDARD=LVCMOS33;
Net sys_rst_pin LOC = E9;
Net sys_rst_pin IOSTANDARD=LVCMOS33;
#在芯片内部，通过配置完成sys_rst_pin上拉
Net sys_rst_pin PULLUP;
## System level constraints
#把sys_clk_pin驱动的所有同步元件定义为一个名为sys_clk_pin的分组
Net sys_clk_pin TNM_NET = sys_clk_pin;
#定义sys_clk_pin的时钟周期为10000 ps，默认的占空比为50%
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
#忽略sys_rst_pin上的时序问题
Net sys_rst_pin TIG;
Net fpga_0_SRAM_CLK LOC=G8;
#配置fpga_0_SRAM_CLK管脚电平变化的速率为FAST
Net fpga_0_SRAM_CLK SLEW = FAST;
#指定输出驱动的强度为12
Net fpga_0_SRAM_CLK DRIVE = 12;
Net fpga_0_SRAM_CLK IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_CLK_FB LOC=AG21;
Net fpga_0_SRAM_CLK_FB IOSTANDARD=LVCMOS33;
## IO Devices constraints
#### Module RS232_Uart_1 constraints
Net fpga_0_RS232_Uart_1_sin_pin LOC = AG15;
Net fpga_0_RS232_Uart_1_sin_pin IOSTANDARD=LVCMOS33;
Net fpga_0_RS232_Uart_1_sout_pin LOC = AG20;
Net fpga_0_RS232_Uart_1_sout_pin IOSTANDARD=LVCMOS33;
#### Module LEDs_8Bit constraints
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC = AE24;
##为fpga_0_LEDs_8Bit_GPIO_IO_pin<0>指定一个电平标准LVCMOS18
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD=LVCMOS18;
#在芯片内部，通过配置完成sys_rst_pin下拉
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> PULLDOWN;
#配置fpga_0_LEDs_8Bit_GPIO_IO_pin<0>管脚电平变化的速率为SLOW
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> SLEW=SLOW;
#指定输出驱动的强度为2
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC = AD24;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD=LVCMOS18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC = AD25;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD=LVCMOS18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC = G16;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD=LVCMOS25;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC = AD26;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD=LVCMOS18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC = G15;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD=LVCMOS25;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC = L18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD=LVCMOS25;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC = H18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD=LVCMOS25;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> DRIVE=2;
# EMAC0 Clocking
# EMAC0 TX Client Clock input from BUFG
#把*/tx_client_clk*驱动的所有同步元件定义为一个名为clk_client_tx0的分组
NET "*/tx_client_clk*" TNM_NET = "clk_client_tx0";
#将clk_client_tx0形成一个新的分组v5_emac_v1_3_single_gmii_client_clk_tx0
TIMEGRP "v5_emac_v1_3_single_gmii_client_clk_tx0" = "clk_client_tx0";
#定义v5_emac_v1_3_single_gmii_client_clk_tx0的时钟周期为7700 ps，开始为高电平，占空比为50%
TIMESPEC "TS_v5_emac_v1_3_single_gmii_client_clk_tx0" = PERIOD "v5_emac_v1_3_single_gmii_client_clk_tx0" 7700 ps HIGH 50 %;
# EMAC0 RX Client Clock input from BUFG
#把*/rx_client_clk*驱动的所有同步元件定义为一个名为clk_client_rx0的分组
NET "*/rx_client_clk*" TNM_NET = "clk_client_rx0";
#将clk_client_rx0形成一个新的分组v5_emac_v1_3_single_gmii_client_clk_rx0
TIMEGRP "v5_emac_v1_3_single_gmii_client_clk_rx0" = "clk_client_rx0";
#定义v5_emac_v1_3_single_gmii_client_clk_rx0的时钟周期为7700 ps，开始为高电平，占空比为50%
TIMESPEC "TS_v5_emac_v1_3_single_gmii_client_clk_rx0" = PERIOD "v5_emac_v1_3_single_gmii_client_clk_rx0" 7700 ps HIGH 50 %;
# EMAC0 TX PHY Clock input from BUFG
#把*/tx_gmii_mii_clk*驱动的所有同步元件定义为一个名为clk_phy_tx0的分组
NET "*/tx_gmii_mii_clk*" TNM_NET = "clk_phy_tx0";
TIMEGRP "v5_emac_v1_3_single_gmii_phy_clk_tx0" = "clk_phy_tx0";
TIMESPEC "TS_v5_emac_v1_3_single_gmii_phy_clk_tx0" = PERIOD "v5_emac_v1_3_single_gmii_phy_clk_tx0" 7700 ps HIGH 50 %; |
