|
- UID
- 852722
|
-- The Following Information Has Been Generated By Exemplar Logic And May Be Freely Distributed And Modified.
-- Design Name : Pseudorandom Purpose : This Design Is A Pseudorandom Number Generator. This Design Will Generate An 8-Bit Random Number Using The Polynomial P(X) = X + 1.
-- This System Has A Seed Generator And Will Generate 2**8 - 1 Unique
-- Vectors In Pseudorandom Order. These Vectors Are Stored In A RAM Which
-- Samples The Random Number Every 32 Clock Cycles. This Variance Of A
-- Priority Encoded Seed Plus A Fixed Sampling Frequency Provides A Truely
-- Random Number.
--
-- This Design Used VHDL-1993 Methods For Coding VHDL.
--
Library IEEE ;
Use IEEE.Std_logic_1164.All ;
Use IEEE.Std_logic_arith.All ;
Entity Divide_by_n Is
Generic (Data_width : Natural := 8 );
Port (
Data_in : In UNSIGNED(Data_width - 1 Downto 0) ;
Load : In Std_logic ;
Clk : In Std_logic ;
Reset : In Std_logic ;
Divide : Out Std_logic
);
End Divide_by_n ;
Architecture Rtl Of Divide_by_n Is
Signal Count_reg : UNSIGNED(Data_width - 1 Downto 0) ;
Constant Max_count : UNSIGNED(Data_width - 1 Downto 0) := (Others => ''1'') ;
Begin
Cont_it : Process(Clk,Reset)
Begin
If (Reset = ''1'') Then
Count_reg <= (Others => ''0'') ;
Elsif (Clk = ''1'' And Clk''Event) Then
If (Load = ''1'') Then
Count_reg <= Data_in ;
Else
Count_reg <= Count_reg + "01" ;
End If ;
End If;
End Process ;
Divide <= ''1'' When Count_reg = Max_count Else ''0'' ;
End RTL ;
Library IEEE ;
Use IEEE.Std_logic_1164.All ;
Use IEEE.Std_logic_arith.All ;
Entity Dlatrg Is
Generic (Data_width : Natural := 16 );
Port (
Data_in : In UNSIGNED(Data_width - 1 Downto 0) ;
Clk : In Std_logic ;
Reset : In Std_logic ;
Data_out : Out UNSIGNED(Data_width - 1 Downto 0)
);
End Dlatrg ;
Architecture Rtl Of Dlatrg Is
Begin
Latch_it : Process(Data_in,Clk,Reset)
Begin
If (Reset = ''1'') Then
Data_out <= (Others => ''0'') ;
Elsif (Clk = ''1'') Then
Data_out <= Data_in ;
End If;
End Process ;
End RTL ;
Library IEEE ;
Use IEEE.Std_logic_1164.All ;
Use IEEE.Std_logic_arith.All ;
Entity Lfsr Is
Generic (Data_width : Natural := 8 );
Port (
Clk : In Std_logic ;
Reset : In Std_logic ;
Data_out : Out UNSIGNED(Data_width - 1 Downto 0)
);
End Lfsr ;
Architecture Rtl Of Lfsr Is
Signal Feedback : Std_logic ;
Signal Lfsr_reg : UNSIGNED(Data_width - 1 Downto 0) ;
Begin
Feedback <= Lfsr_reg(7) Xor Lfsr_reg(0) ;
Latch_it : Process(Clk,Reset)
Begin
If (Reset = ''1'') Then
Lfsr_reg <= (Others => ''0'') ;
Elsif (Clk = ''1'' And Clk''Event) Then
Lfsr_reg <= Lfsr_reg(Lfsr_reg''High - 1 Downto 0) & Feedback ;
End If;
End Process ;
Data_out <= Lfsr_reg ;
End RTL ;
Library IEEE ;
Use IEEE.Std_logic_1164.All ;
Use IEEE.Std_logic_arith.All ;
Entity Priority_encoder Is
Generic (Data_width : Natural := 25 ;
Address_width : Natural := 5 ) ;
Port (
Data : In UNSIGNED(Data_width - 1 Downto 0) ;
Address : Out UNSIGNED(Address_width - 1 Downto 0) ;
None : Out STD_LOGIC
);
End Priority_encoder ;
Architecture Rtl Of Priority_encoder Is
Attribute SYNTHESIS_RETURN : STRING ;
FUNCTION To_stdlogic (Arg1:BOOLEAN) RETURN STD_LOGIC IS
BEGIN
IF(Arg1) THEN
RETURN(''1'') ;
ELSE
RETURN(''0'') ;
END IF ;
END ; |
|
