Altera的MAX-II(EPM240T100C5)内部FLASH的读写逻辑(采用总
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Altera的MAX-II(EPM240T100C5)内部FLASH的读写逻辑(采用总
MAX-II内部自带的FLASH(确切的说,应该是一个EEPROM,类似于ATMEL的24XX系列)可采用3种接口方式:I2C、SPI和总线接口。前两种为串行模式,在QUARTUSII软件中Altera已经提供了IP模块,但是没有提供总线读写逻辑。下面实现的是一个总线接口读写模式的逻辑。语言采用Verilog编写。系统平台采用ARM9。
//片选译码,flash_erase_cs为擦除命令的片选,flash_cs为读写命令的片选
wireflash_cs;
wireflash_erase_cs;
assignflash_erase_cs = !(!nGcs4 & laddr24 & !laddr[6] &laddr[5] &!laddr[4] & !laddr[3] & !laddr[2]
&laddr[1] & !laddr[0]);
assignflash_cs = !(!nGcs5 &laddr24);
//状态机逻辑,用于将读写时序拉长至600ns以上
//clkout0为50MHz的时钟
//userflash逻辑
regflash_rdy;
reg [1:0]flash_state;
reg [4:0]flash_counter;
parameterFLASH_SUM=5'b11110;
parameterFLASH_T1=2'b00,FLASH_T2=2'b01,FLASH_T3=2'b10;
always@(posedge clkout0 or negedge nReset)
begin
if(!nReset)begin
flash_rdy<= 1'b1;
flash_counter <= 5'b0;
flash_state<= FLASH_T1;
end
elsebegin
case(flash_state)
FLASH_T1:begin
if((!flash_cs)||(!flash_erase_cs)) begin
flash_rdy<= 1'b0;
flash_state<= FLASH_T2;
end
else
flash_state<= FLASH_T1;
end
FLASH_T2:begin
flash_counter <= flash_counter + 5'b1;
if(flash_counter > FLASH_SUM)
flash_state<= FLASH_T3;
else
flash_state<= FLASH_T2;
end
FLASH_T3:begin
flash_rdy<= 1'b1;
flash_counter <= 5'b0;
flash_state<= FLASH_T1;
end
default:begin
flash_rdy<= 1'b1;
flash_counter <= 5'b0;
flash_state<= FLASH_T1;
end
endcase
end
end
assignnWait = flash_rdy;
assignnread = !(!lnoe & !flash_cs);
assignnwrite = !(!lnwe & !flash_cs);
assignnerase = !(!lnwe & !flash_erase_cs);
assign dout= (!nwrite) ? sd : 8'b11111111;
assign sd =(!kb_cs) ? ps2_p_data[7:0] :
((!nread) ?din : 8'bzzzzzzzz); |
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