基于FPGA的LCD1602动态显示---Verilog实现(3)
- UID
- 1029342
- 性别
- 男
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基于FPGA的LCD1602动态显示---Verilog实现(3)
//--------------------work state-------------------- 5'd8: begin
lcd_rs <= 1'b0;
lcd_en <= 1'b1;
lcd_data <= addr; //write addr
state <= state + 1'd1;
end
5'd9: begin
lcd_en <= 1'b0;
state <= state + 1'd1;
end
5'd10: begin
lcd_rs <= 1'b1;
lcd_en <= 1'b1;
lcd_data <= "C"; //write data
state <= state + 1'd1;
end
5'd11: begin
lcd_en <= 1'b0;
state <= state + 1'd1;
end
5'd12: begin
lcd_rs <= 1'b1;
lcd_en <= 1'b1;
lcd_data <= "n"; //write data
state <= state + 1'd1;
end
5'd13: begin
lcd_en <= 1'b0;
state <= state + 1'd1;
end
5'd14: begin
lcd_rs <= 1'b1;
lcd_en <= 1'b1;
lcd_data <= "t"; //write data
state <= state + 1'd1;
end
5'd15: begin
lcd_en <= 1'b0;
state <= state + 1'd1;
end
5'd16: begin
lcd_rs <= 1'b1;
lcd_en <= 1'b1;
lcd_data <= ":"; //write data
state <= state + 1'd1;
end
5'd17: begin
lcd_en <= 1'b0;
state <= state + 1'd1;
end
5'd18: begin
lcd_rs <= 1'b1;
lcd_en <= 1'b1;
lcd_data <= data1; //write data: tens digit
state <= state + 1'd1;
end
5'd19: begin
lcd_en <= 1'b0;
state <= state + 1'd1;
end
5'd20: begin
lcd_rs <= 1'b1;
lcd_en <= 1'b1;
lcd_data <= data0; //write data: single digit
state <= state + 1'd1;
end
5'd21: begin
lcd_en <= 1'b0;
state <= 5'd8;
end
default: state <= 5'bxxxxx;
endcase
end
end
assign lcd_rw = 1'b0; //only write
//------------------backlight driver----------------
assign lcd_n = 1'b0;
assign lcd_p = 1'b1;
endmodule |
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