MicroBlaze的总线接口
MicroBlaze支持的外设接口示意图
CoreConnect是由IBM开发的片上总线通信链，它使多个源的芯片核相互连接成为一个完整的新芯片成为可能。CoreConnect技术使整合变得更为容易，而且在标准产品平台设计中处理器、系统以及外围的核可以重复使用，以达到更高的整体系统性能。
MicroBlaze v7.0软核支持的借口标准
? A 32-bit version of the PLB V4.6 interface (see IBM’s 128-Bit Processor Local Bus Architectural Specifications, Version 4.6).
? A 32-bit version of the OPB V2.0 bus interface (see IBM’s 64-Bit On-Chip Peripheral Bus, Architectural Specifications, Version 2.0)
?LMB provides simple synchronous protocol for efficient block RAM transfers
? FSL provides a fast non-arbitrated streaming communication mechanism
?XCL provides a fast slave-side arbitrated streaming interface between caches and external memory controllers
?Debug interface for use with the Microprocessor Debug Module (MDM) core
?Trace interface for performance analysis
MicroBlaze内部总线结构
DPLB:
Data interface, Processor LocalBus
DOPB: Data interface, On-chip Peripheral Bus
DLMB:
Data interface, Local Memory Bus (BRAM only)
IPLB: Instruction interface, Processor Local Bus
IOPB:
Instruction interface, On-chip Peripheral Bus
ILMB: Instruction interface, Local Memory Bus (BRAM only)
MFSL 0..15:
FSL master interfaces
SFSL 0..15:
FSL slave interfaces
IXCL: Instruction side Xilinx CacheLink interface (FSL master/slave pair)
DXCL:
Data side Xilinx CacheLink interface (FSL master/slave pair)
Core: Miscellaneous signals for: clock, reset, debug, and trace |
