部分代码：
//Date :2012-5-27
//Description : 8 阶FIR滤波器 ，通带2MH，阻带8MHz，带外衰减80dB,通带波动1dB
//Uesedfor
//Taobao :
//E-mail :2352517093@qq.com
//==========================================================================
`timescale 1 ns / 1 ns
module fir_filter
(
i_fpga_clk ,
i_rst_n ,
i_filter_in,
o_filter_out
);
input i_fpga_clk ; //25MHz
input i_rst_n ;
inputsigned [7:0] i_filter_in ; //数据速率25Mh
output reg signed [7:0] o_filter_out; //滤波输出
//==============================================================
//8阶滤波器系数，共9个系数，系数对称
//==============================================================
wire signed[15:0] coeff1 = 16'd239 ;
wire signed[15:0] coeff2 = 16'd1507;
wire signed[15:0] coeff3 = 16'd4397;
wire signed[15:0] coeff4 = 16'd7880;
wire signed[15:0] coeff5 = 16'd9493;
//===============================================================
//延时链
//===============================================================
reg signed [7:0] delay_pipeline1 ;
reg signed [7:0] delay_pipeline2 ;
reg signed [7:0] delay_pipeline3 ;
reg signed [7:0] delay_pipeline4 ;
reg signed [7:0] delay_pipeline5 ;
reg signed [7:0] delay_pipeline6 ;
reg signed [7:0] delay_pipeline7 ;
reg signed [7:0] delay_pipeline8 ;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n)
if(!i_rst_n)
begin
delay_pipeline1 <= 8'b0 ;
delay_pipeline2 <= 8'b0 ;
delay_pipeline3 <= 8'b0 ;
delay_pipeline4 <= 8'b0 ;
delay_pipeline5 <= 8'b0 ;
delay_pipeline6 <= 8'b0 ;
delay_pipeline7 <= 8'b0 ;
delay_pipeline8 <= 8'b0 ;
end
else
begin
delay_pipeline1 <=i_filter_in ;
delay_pipeline2 <= delay_pipeline1 ;
delay_pipeline3 <= delay_pipeline2 ;
delay_pipeline4 <= delay_pipeline3 ;
delay_pipeline5 <= delay_pipeline4 ;
delay_pipeline6 <= delay_pipeline5 ;
delay_pipeline7 <= delay_pipeline6 ;
delay_pipeline8 <= delay_pipeline7 ;
end
//================================================================
//加法，对称结构，减少乘法器的数目
//================================================================
reg signed [8:0] add_data1 ;
reg signed [8:0] add_data2 ;
reg signed [8:0] add_data3 ;
reg signed [8:0] add_data4 ;
reg signed [8:0] add_data5 ;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //x(0)+x(8)
if(!i_rst_n)
add_data1 <= 9'b0 ;
else
add_data1 <= i_filter_in + delay_pipeline8 ;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //x(1)+x(7)
if(!i_rst_n)
add_data2 <= 9'b0;
else
add_data2 <= delay_pipeline1 + delay_pipeline7;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //x(2)+x(6)
if(!i_rst_n)
add_data3 <= 9'b0;
else
add_data3 <= delay_pipeline2 + delay_pipeline6;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk ornegedge i_rst_n) //x(3)+x(5)
if(!i_rst_n)
add_data4 <= 9'b0;
else
add_data4 <= delay_pipeline3 + delay_pipeline5;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //x(4)
if(!i_rst_n)
add_data5 <= 9'b0;
else
add_data5 <= {delay_pipeline4[7],delay_pipeline4};
//===================================================================
//乘法器
//====================================================================
reg signed [24:0] multi_data1 ;
reg signed [24:0] multi_data2 ;
reg signed [24:0] multi_data3 ;
reg signed [24:0] multi_data4 ;
reg signed [24:0] multi_data5 ;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //（x(0)+x(8)）*h(0)
if(!i_rst_n)
multi_data1 <= 24'b0 ;
else
multi_data1 <= add_data1*coeff1 ;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //（x(1)+x(7)）*h(1)
if(!i_rst_n)
multi_data2 <= 24'b0 ;
else
multi_data2 <= add_data2*coeff2 ;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //（x(2)+x(6)）*h(2)
if(!i_rst_n)
multi_data3 <= 24'b0 ;
else
multi_data3 <= add_data3*coeff3 ;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //（x(0)+x(8)）*h(3)
if(!i_rst_n)
multi_data4 <= 24'b0 ;
else
multi_data4 <= add_data4*coeff4 ;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //x(4)*h(4)
if(!i_rst_n)
multi_data5 <= 24'b0 ;
else
multi_data5 <= add_data5*coeff5 ;
//========================================================================
//流水线累加
//========================================================================
reg signed[25:0] add_level1_1;//1级
reg signed[25:0] add_level1_2;//1级
reg signed[25:0] add_level1_3;//1级
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //（x(0)+x(8)）*h(0)+（x(1)+x(7)）*h(1)
if(!i_rst_n)
add_level1_1 <= 26'b0 ;
else
add_level1_1 <= multi_data1+multi_data2 ;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //（x(2)+x(6)）*h(2)+（x(3)+x(5)）*h(3)
if(!i_rst_n)
add_level1_2 <= 26'b0 ;
else
add_level1_2 <= multi_data3+multi_data4 ;
[email=always@%28posedge]always@(posedge[/email] i_fpga_clk or negedgei_rst_n) //x(4)*h(4)
if(!i_rst_n)
add_level1_3 <= 26'b0 ;
else
add_level1_3 <={multi_data5[24],multi_data5} ;
//==2级加法 | 
