library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity displayc is port( clk : in std_logic; indata : in std_logic_vector(7 downto 0); reset : in std_logic; cs2 : out std_logic; rw : out std_logic; dc : out std_logic; addr : out std_logic_vector(2 downto 0); outdata : out std_logic_vector(7 downto 0)); end; architecture sdisplayc of displayc is type state_type is (idle,playon,duty,adc,res,page,clum,wdata); signal state : state_type; signal flag : std_logic; signal cnt : std_logic_vector(2 downto 0); begin cs2<='0'; rw<='0'; dc<='1' when state=wdata else '0'; addr<=cnt when state=wdata else "ZZZ"; outdata<= "10101111" when state=playon else "10101001" when state=duty else "10100000" when state=adc else "11100010" when state=res else "10111010" when state=page else "00000000" when state=clum else indata when state=wdata else "ZZZZZZZZ"; process(clk,reset) begin if reset='0' then state<=idle; flag<='0'; cnt<="000"; elsif clk'event and clk='1' then case state is when idle => if flag='0' then flag<='1'; cnt<="000"; state<=playon; else state<=idle; end if; when playon => state<=duty; when duty => state<=adc; when adc => state<=res; when res => state<=page; when page => state<=clum; when clum => state<=wdata; when wdata => if cnt="111" then state<=idle; else cnt<=cnt+1; state<=wdata; end if; end case; end if; end process; end sdisplayc; 然后例化16次即可。 |