小弟初学 verilog 各位高手们帮帮忙 程序如下 module jishu(clk,rst,data_in,data_out);
input clk,rst;
input [7:0] data_in;
output data_out;
integer i; reg data_out;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
data_out<=0;
end
else
begin
for(i=0;i<=7;i=i+1)
data_out<=data_in;
end
end
endmodule 不知道那个输入 data_in 怎么定义 它老是出现警告 ignored unnecesary INPUT pin'data_in7 ignored unnecesary INPUT pin'data_in6 ignored unnecesary INPUT pin'data_in5 ignored unnecesary INPUT pin'data_in4 ignored unnecesary INPUT pin'data_in3 ignored unnecesary INPUT pin'data_in2 ignored unnecesary INPUT pin'data_in1 ignored unnecesary INPUT pin'data_in0 各位帮帮忙 毕社中重要的一部分 | 
