[求助] 几个VHDL的警告错误 VHDL, 警告, 求助

qujjun

Warning: LATCH primitive "wal[3]$latch" is permanently disabled

Warning: Design contains 1 input pin(s) that do not drive logic
 Warning: No output dependent on input pin "clk"

lsy810809

1。锁存的enable接地了

2。有个输入引脚和内部逻辑无关

3。估计你使用的都是组合逻辑，和时钟无关

随便乱说，高手指正