module MYFX2 (
nRESET,// Inputs from FX2
PA,
KEY,
MMCLK, //from cytal
LED, // LED indicator
GPD, CTL,RDY
);
//////////////////////////////////
inout [15:0]GPD; input [2:0]CTL;
output [1:0]RDY;
reg [1:0]RDY;
////////////////////////////////////////////
input nRESET;
///////////////////////////////////
input [3:0]KEY;
inout [7:0]PA;
////////////////////////////////// input MMCLK; output [3:0]LED;
reg [3:0]LED; reg [15:0]DREG;
reg BLable;
//output USBCLK;
reg [1:0] STATE,NEXT;
reg CLK_2,CLK_4,CLK_8;
wire HCLK; parameter IDLE = 2'D0,
WRITE_1 = 2'D1,
WRITE_2 = 2'D2;
assign PA[4]=0;
assign PA[5]=1;
assign GPD[15:0]=RDY[1]? 'hz  REG[15:0];
always @(posedge MMCLK)
begin
CLK_2 <= ~CLK_2;
end always @(posedge CLK_2)
begin
CLK_4 <= ~CLK_4;
end
always @(posedge CLK_4)
begin
CLK_8 <= ~CLK_8;
end
assign HCLK = CLK_8;
//state machine
always @ (STATE or LED[0])
begin
case(STATE)
IDLE : if(LED[0])
NEXT = WRITE_1;
else
NEXT = IDLE ;
WRITE_1 : NEXT = WRITE_2;
WRITE_2 :
NEXT = WRITE_1;
default : NEXT = IDLE ;
endcase
end
//registe the state
always @(posedge HCLK or negedge nRESET)
if(!nRESET)
begin
STATE <= IDLE;
end
else
STATE <= NEXT;
always @(posedge HCLK or negedge nRESET)
if(!nRESET)
begin
DREG <=16'hffff;
RDY[1] <=1'b1;
RDY[0] <=1'b1;
LED[0] <= 1'b1;
// BLable=1;
end
else
case(STATE)
IDLE : begin
RDY[0] <= 1;
RDY[1] <= 1;
end
WRITE_1 : begin
// if (BLable==1)
// begin
DREG <= DREG+1;
// if (DREG==255) BLable=0;
// end
// if (BLable==0)
// begin
// DREG <= DREG-1;
// if (DREG==0) BLable=1;
// end
RDY[1] <= 1'b0;
RDY[0] <= 1'b1;
end
WRITE_2 : begin
RDY[1] <= 1'b1;
RDY[0] <= 1'b1; end
endcase | 
