[求助]不能综合，大家帮忙看一下，谢谢！ 求助, 帮忙

wlj3304

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
 generic(width:integer:=16);
     Port (trig: in  STD_LOGIC;
         
           resetn : in  STD_LOGIC;
      
           CS : in  STD_LOGIC;    
     Slk  : in  STD_LOGIC;
           Dout : out  STD_LOGIC;
           ACK : inout  STD_LOGIC);
end test;
architecture Behavioral of test is  
 
   signal shift_buf: std_logic_vector(width-1 downto 0);
 begin
loadshift:process(resetn,trig,count_outQ)  
begin
    if resetn='0' then
         shift_buf<=(others=>'0');
   elsif (ACK='1') then
      shift_buf<=count_outQ;
   end if;
end process loadshift;
shifter:process(Slk)  
begin
     if (Slk'event and Slk='1') then
     elsif CS='1' then   
        shift_buf<=shl(shift_buf,"1");
        shift_buf(0)<='0';
       end if;
 
end process shifter;
       Dout<=shift_buf(width-1);
end behavioral;
提示错误：Signal shift_buf<10> cannot be synthesized, bad synchronous description.
大家帮忙看一下谢谢！该程序的简单功能就是计数器的结果并入移位寄存器，然后是移位输出受到外部信号slk和总线使能信号cs的控制输出，

不受其他控制

iamzhr

 if (Slk'event and Slk='1') then
     elsif CS='1' then   
        shift_buf<=shl(shift_buf,"1");
        shift_buf(0)<='0';
       end if;

第一行的then后面怎么没有语句啊，语法不对啊，据我对你程序的理解应该改成

if (Slk'event and Slk='０') then
     if CS='1' then   
        shift_buf<=shl(shift_buf,"1");
        shift_buf(0)<='0';
       end if;

end if;