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[求助]关于综合的问题

[求助]关于综合的问题

各位高手:有个问题想请教大家! 我的一个类似双端口RAM的一个程序 但是只作为一个通道使用,开辟的空间是16位的 大小为4K 分为2块 MEM0[15:8] MEM1[7:0]编译没有错误 但是综合时也没有报告错误!只不过是一直在哪里综合 没有综合成功 也不显示错误!请求高手指点米!!!!万分感激 这个是报告

*                          HDL Compilation                              *
=========================================================================
Compiling source file "/../../../../../../Modeltech_xe/examples/txinterface0723.v"
Module <ethtxinterface> compiled
No errors in compilation
Analysis of file <ethtxinterface.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:258 - /../../../../../../Modeltech_xe/examples/txinterface0723.v line 71 Range on redeclaration of 'addrout' overrides range on output declaration at /../../../../../../Modeltech_xe/examples/txinterface0723.v line 23
Analyzing top module <ethtxinterface>.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
WARNING:Xst:916 - /../../../../../../Modeltech_xe/examples/txinterface0723.v line 453: Delay is ignored for synthesis.
WARNING:Xst:916 - /../../../../../../Modeltech_xe/examples/txinterface0723.v line 461: Delay is ignored for synthesis.
Module <ethtxinterface> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <action> in unit <ethtxinterface> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <ethtxinterface>.
    Related source file is /../../../../../../Modeltech_xe/examples/txinterface0723.v.
WARNING:Xst:647 - Input <selwbin> is never used.
WARNING:Xst:647 - Input <oea> is never used.
WARNING:Xst:1780 - Signal <do5> is never used or assigned.
WARNING:Xst:1780 - Signal <do6> is never used or assigned.
WARNING:Xst:1780 - Signal <addrreg> is never used or assigned.
WARNING:Xst:646 - Signal <action> is assigned but never used.
WARNING:Xst:1780 - Signal <do11> is never used or assigned.

各位高手:有个问题想请教大家! 我的一个类似双端口RAM的一个程序 但是只作为一个通道使用,开辟的空间是数据是16位的,地址线是12位    大小为4K 分为2块 MEM0[15:8] MEM1[7:0]编译没有错误 但是综合时也没有报告错误!只不过是一直在哪里综合 没有综合成功 也不显示错误!请求高手指点米!!!!万分感激 这个是报告

*                          HDL Compilation                              *
=========================================================================
Compiling source file "/../../../../../../Modeltech_xe/examples/txinterface0723.v"
Module <ethtxinterface> compiled
No errors in compilation
Analysis of file <ethtxinterface.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:258 - /../../../../../../Modeltech_xe/examples/txinterface0723.v line 71 Range on redeclaration of 'addrout' overrides range on output declaration at /../../../../../../Modeltech_xe/examples/txinterface0723.v line 23
Analyzing top module <ethtxinterface>.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem1> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <mem0> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
WARNING:Xst:916 - /../../../../../../Modeltech_xe/examples/txinterface0723.v line 453: Delay is ignored for synthesis.
WARNING:Xst:916 - /../../../../../../Modeltech_xe/examples/txinterface0723.v line 461: Delay is ignored for synthesis.
Module <ethtxinterface> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <action> in unit <ethtxinterface> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <ethtxinterface>.
    Related source file is /../../../../../../Modeltech_xe/examples/txinterface0723.v.
WARNING:Xst:647 - Input <selwbin> is never used.
WARNING:Xst:647 - Input <oea> is never used.
WARNING:Xst:1780 - Signal <do5> is never used or assigned.
WARNING:Xst:1780 - Signal <do6> is never used or assigned.
WARNING:Xst:1780 - Signal <addrreg> is never used or assigned.
WARNING:Xst:646 - Signal <action> is assigned but never used.
WARNING:Xst:1780 - Signal <do11> is never used or assigned.
  综合到这里的时候就过不去了 不知道为什么! 4K的RAM数据线16位 地址线12位
 

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