各位大侠， 想仿真一下IP core ，但在之前的Compile HDL simulation Libraries 时，Project navagitor给出错误信息。 ** Error: (vcom-19) Failed to access library 'xilinxcorelib' at "xilinxcorelib". No such file or directory. (errno = ENOENT) 我是根据XILINX相关文档上做的，但不知还缺少了什么步骤。 ____ ____
/ /\/ /
/___/ \ / VENDOR : Xilinx Inc.
\ \ \/ VERSION : 9.1i (J.30)
\ \ APPLICATION : compxlib
/ / CONTENTS : Compilation Log
/___/ /\ FILENAME : compxlib.log
\ \ / \ CREATED ON : Tue Jul 31 20:03:48 2007
\___\/\___\ XILINX = 'C:\Xilinx91i'
Library Source => 'C:\Xilinx91i' Compilation Mode = FAST
Scheduling library compilation for AUTOMOTIVE SPARTAN-III Signature:-
------------------------------------------------------------------------------
compxlib -s mti_se
-arch aspartan3
-lib xilinxcorelib
-l vhdl
-dir E:\my job\FPGA Practise\xilinxcorelibb
-log compxlib.log
-w
-p C:/Modeltech_6.0/win32
------------------------------------------------------------------------------
Compiling Xilinx HDL Libraries for ModelSim SE Simulator
Language => vhdl
Backing up setup files if any...
Output directory => 'E:\my job\FPGA Practise\xilinxcorelibb' --> Compiling vhdl XilinxCoreLib library
> compiling unisim library first
> Unisim compiled to E:\my job\FPGA Practise\xilinxcorelibb\unisim ============================================================================== Modifying modelsim.ini Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling package vcomponents Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package textio
-- Loading package std_logic_1164
-- Loading package vital_timing
-- Loading package vital_primitives
-- Compiling package vpkg
-- Compiling package body vpkg
-- Loading package vpkg Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity and2
-- Compiling architecture and2_v of and2
-- Compiling entity and2b1
-- Compiling architecture and2b1_v of and2b1
-- Compiling entity and2b2
。。。。。。。。。。。。。 。。。。。。。。。。。。
-- Loading package numeric_std
-- Compiling entity dataflash
-- Compiling architecture design of dataflash
-- Loading package vital_primitives
-- Loading package vpkg
-- Compiling entity spi_access
-- Compiling architecture spi_access_v of spi_access
-- Compiling entity startup_spartan3a
-- Compiling architecture startup_spartan3a_v of startup_spartan3a ============================================================================== > Log file E:\my job\FPGA Practise\xilinxcorelibb\unisim\cxl_unisim.log generated
> Library mapping successful, setup file(s) modelsim.ini updated
> [unisim]: No error(s), no warning(s)
> XilinxCoreLib compiled to E:\my job\FPGA Practise\xilinxcorelibb\XilinxCoreLib ============================================================================== Modifying modelsim.ini Usage: vmap [-help] [-c] [-del] [<logical_name>] [<path>] Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package textio
-- Loading package std_logic_1164
-- Compiling package iputils_conv
-- Compiling package body iputils_conv
-- Loading package iputils_conv
-- Compiling package decode_8b10b_v7_1_pkg
-- Compiling package body decode_8b10b_v7_1_pkg
-- Loading package decode_8b10b_v7_1_pkg
** Error: (vcom-19) Failed to access library 'xilinxcorelib' at "xilinxcorelib".
No such file or directory. (errno = ENOENT) ============================================================================== > Log file E:\my job\FPGA Practise\xilinxcorelibb\XilinxCoreLib\cxl_XilinxCoreLib.log generated
> Library mapping successful, setup file(s) modelsim.ini updated compxlib[XilinxCoreLib]: 1 error(s), no warning(s) **************************************************************************
* COMPILATION SUMMARY *
* *
* Simulator used: mti_se *
* Compiled on: Tue Jul 31 20:06:19 2007 *
* *
**************************************************************************
* Library | Lang | Mapped Name(s) | Err#(s) | Warn#(s) *
*------------------------------------------------------------------------*
* unisim | vhdl | unisim | 0 | 0 *
*------------------------------------------------------------------------*
* XilinxCoreLib | vhdl | XilinxCoreLib | 1 | 0 *
*------------------------------------------------------------------------*
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