同步时钟采样模块：为的是使得外部输入的异步信号需要经过系统时钟的同步化，且将输入的异步信号整形成一个时钟长的脉冲信号。
module clk_syn( clk,rst,s_in,s_out );
input wire clk;
input wire rst;
input wire s_in;
output wire s_out;
reg s_t1,s_t2;
always@(posedge clk)begin
if(!rst) begin
s_t1 <= 0;
s_t2 <= 0;
end
else begin
s_t1 <= s_in;
s_t2 <= s_t1;
end
end
assign s_out = s_t1 & (~s_t2);
endmodule |
