ERROR:HDLCompilers:27 - "start_module.v" line 2 Illegal redeclaration of 'start_module' 我写了两个模块，现写了一个顶层模块要把它们联起来，好写测试用，可是要检查这个TOP文件语法时，出现上面的错误。 TOP文件如下 ： `timescale 1ns / 1ns
`include "state.v"
`include "start_module.v" module start_top(clock,reset,init_evoke,start_work,start_evoke, key_start, scan_work,scan_evoke);
input clock, reset;
output init_evoke, start_work,start_evoke, scan_evoke,scan_work, key_start;
reg init_evoke, start_work,start_evoke, scan_evoke,scan_work, key_start; state A(clock,reset,init_evoke,start_work,start_evoke,scan_work,scan_evoke); //state 是这前定义过的模块
start_module B (reset,start_evoke,key_startscan_work); //start_module endmodule
其中start_module定义如下： `timescale 1ns / 1ns
module start_module(reset,start_evoke, key_start, scan_work);
input reset;
input start_evoke;
input key_start;
output scan_work;
reg scan_work;
always @(posedge key_start or posedge start_evoke or negedge reset)
begin
if(!reset) scan_work = 0;
else if ((start_evoke == 1)&(key_start == 1))
begin
scan_work = 1;
end
end
endmodule
大家帮忙看看这是什么错误
[此贴子已经被作者于2007-10-6 11:19:16编辑过] | 
