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DSP design Engineer
Description: The candidate will join a team of algorithm design and FPGA prototyping involved in the development of advanced digital signal processing algorithm for the physical layer of high speed wired data communication IC.
Responsibility: l
Design and develop PAM/QAM single/Multi-carrier transceivers, multi-input adaptive equalizers/echo cancellers, multi-dimentional trellis encoder/decoder, timing recovery, digital filters, interface with analog blocks and MAC/switch blocks. l
Create bit-exact Matlab/C system model and perform simulation. l
Design and simulate verilog RTL code using synopsys and cadence EDA tools. l
Prototype, debug and verify RTL code on Xilinx multi-FPGA platform. l
Perform coding, synthesis, timing closure, placement and route on FPGA.
Job Requirements: l
MSEE.or Ph.D. With 5+ years of experience in developing, implementing, and debugging high-performance communications and DSP ASIC products. l
Strong academic background of digital communication theory with proficient Matlab/C programming and simulation skills. l
Extensive verilog RTL experience including design, verification, synthesis, and debugging. l
Proficiency of Xilinx FPGA prototyping. l
Solid hands-on experience of using different lab equipment such as oscilloscopes, logic analyzer, signal generator, spectrum analyzer, etc. l
Fluency in English reading and writing. l
IEEE 802.3 or previous Ethernet product development experience is a plus. | 
