- UID
- 86764
- 性别
- 男
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我的程序出了问题,请各位大侠不吝赐教:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity V4_3 is
port(aIn : in bit_vector(7 downto 0);
sllout : out bit_vector(7 downto 0));
end V4_3;
architecture a of V4_3 is
begin
sllout <= aIn sll '2';
end a;[em06] |
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