大虾帮我看看这个锁存器的VHDL程序 VHDL, 锁存器, 大虾, 程序

wdwong

接了两个锁存器，一个输入，一个输出，a为地址 程序如下：(时序一直通不过） library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity lach is port ( d:INOUT std_logic_vector(15 downto 0); qin:in std_logic_vector(15 downto 0); qoutut std_logic_vector(15 downto 0); a:in std_logic_vector(3 downto 0); s,w,r:in std_logic ); end lach; architecture behave of lach is Signal qind: std_logic_vector(15 downto 0); Signal qoutd: std_logic_vector(15 downto 0); begin process(s) begin if s'event and s='0' then qoutd<=d; qind<=qin; end if; if w='0' and a="1000" then qout<=qoutd; elsif r='0' and a="0010" then d<=qind; end if; end process; end behave;

进程中多加几个敏感信号就ok了    process(s,w,r,d)

library ieee; use ieee.std_logic_1164.all; entity latch373 is port( d:in std_logic_vector(7 downto 0); oe,g:in std_logic; q0,q1,q2,q3,q4,q5,q6,q7ut std_logic --qut std_logic_vector(7 downto 0) ); end latch373; architecture rtl of latch373 is signal q_temp: std_logic_vector(7 downto 0); begin q0<=q_temp(0); q1<=q_temp(1); q2<=q_temp(2); q3<=q_temp(3); q4<=q_temp(4); q5<=q_temp(5); q6<=q_temp(6); q7<=q_temp(7); process(oe,g,d) begin if(oe='0')then if(g='1')then q_temp<=d; end if; else q_temp<="zzzzzzzz";这个地方有问题，而且大小写不一样的错 end if; end process; end rtl; 哪位大侠帮忙看看阿