Rst_Bit_Cnt: LDA #!8 ;Bit counter
Hold_Low: BRCLR 3,PTA,* ;Clock is initially low: wait here.
BRCLR 3,PTA,* ;Debounce
BCLR 2,TBCR ;Mask TBM interrupts.
BCLR 5,TSC ;The timer starts counting here.
BRSET 3,PTA,* ;Clock has gone high: wait for falling edge.
BRSET 3,PTA,* ;Debounce
BRSET 2,PTA,Store_Data ;Falling edge detected: load data into carry bit.
Store_Data: ROL DATA-1,X ;Rotate data from carry into RAM.
BSET 4,TSC ;Reset the timer counter registers.
DBNZA Hold_Low ;Check if a whole byte received.
DBNZX Rst_Bit_Cnt
这是一段spi的程序,他符合模式CPHA =1,cpol=0吗?我认为不符合呀 |