| `timescale 1ns/1ns
module clock(
clk,
reset,
star,
stop,
led,
restar
);
input clk;
input reset;
input star;
input stop;
input restar;
output led;
output [7:0] counter;
reg [7:0] counter;
reg led;
reg [7:0] micstate;
parameter IDLE = 8'h00,
CNTSTAR = 8'h01,
CNTEND = 8'h02,
ACTIVE = 8'h04;
parameter MAXCNT = 8'h40,
MAXLEDCNT = 8'h20;
reg [7:0] ledcnt;
reg led;
always@(posedge clk or posedge reset)
begin
if(reset == 1'[b1)
begin
counter <= 0;
micstate <= IDLE;
ledcnt <= o;
led <= 0;
end
else
begin
case(micstate)
IDLE:
begin
if(star == 1'b1)
micstate <= CNTSTAR;
else
micstate <= IDLE;
end
CNTSTAR:
begin
if(stop == 1'b1)
micstate <= CNTEND;
else if(counter >= MAXCNT)
mimcstate <= ACTIVE;
else
begin
counter <= counter + 1;
micstate <= CNTSTAR;
end
end
CNTEND: micstate <= IDLE;
ACTIVE:
begin
if(restar)
begin
micstate <= IDLE;
end
else
if(ledcnt >=MAXLEDCNT)
begin
ledcnt <= 0;
led <= 1'b1;
end
else
begin
ledcnt <= ledcnt + 1;
led <= 1'b0;
end
end
end
end |
