library ieee;
use ieee.std_logic_1164.all;
entity two is
port(n:in std_logic_vector(3 downto 0);
f ut std_logic
);
end two;
architecture two_arch of two is
begin
process(n)
begin
with n select
f<= '1' when "0001",
'0' when others;
end process;
end two_arch; 这样的小程序，报错1：Error (10500): VHDL syntax error at two.vhd(12) near text "with"; expecting "end", or "(", or an identifier ("with" is a reserved keyword), or a sequential statment 报错2：Error (10500): VHDL syntax error at two.vhd(13) near text "when"; expecting ";" 真是不明白啊，不放在process里就好好的，放进process就有这样的错， 请高手指点啊！！ 谢谢 | 
